參數(shù)資料
型號(hào)： AD9549ABCPZ-REEL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 45/76頁(yè)
文件大?。?/td> 0K
描述： IC CLOCK GEN/SYNCHRONIZR 64LFCSP
產(chǎn)品變化通告： AD9549A Mask Change 22/Oct/2010
標(biāo)準(zhǔn)包裝： 750
類型： 時(shí)鐘/頻率發(fā)生器，同步器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum
輸入： CMOS，LVDS，LVPECL
輸出： CMOS，HSTL
電路數(shù)： 1
比率 - 輸入:輸出： 2:2
差分 - 輸入:輸出： 是/是
頻率 - 最大： 750MHz
電源電壓： 1.71 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 帶卷 (TR)
AD9549
Rev. D | Page 5 of 76
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
SYSTEM CLOCK INPUT
System clock inputs should always be ac-
coupled (both single-ended and differential)
SYSCLK PLL Bypassed
Input Capacitance
1.5
pF
Single-ended, each pin
Input Resistance
2.4
2.6
2.8
k
Differential
Internally Generated DC Bias Voltage2
0.93
1.17
1.38
V
Differential Input Voltage Swing3
632
mV p-p
0 dBm into 50
SYSCLK PLL Enabled
Input Capacitance
3
pF
Single-ended, each pin
Input Resistance
2.4
2.6
2.8
k
Differential
Internally Generated DC Bias Voltage2
0.93
1.17
1.38
V
Differential Input Voltage Swing3
632
mV p-p
0 dBm into 50
Crystal Resonator with SYSCLK PLL Enabled
Motional Resistance
9
100
25 MHz, 3.2 mm × 2.5 mm AT cut
CLOCK OUTPUT DRIVERS
HSTL Output Driver
Differential Output Voltage Swing
1080
1280
1480
mV
Output driver static; see
Figure 12 for output
swing vs. frequency
Common-Mode Output Voltage2
0.7
0.88
1.06
V
CMOS Output Driver
Output driver static; see
Figure 14 for output swing vs. frequency
Output Voltage High (VOH)
2.7
V
IOH = 1 mA, (Pin 37) = 3.3 V
Output Voltage Low (VOL)
0.4
V
IOL = 1 mA, (Pin 37) = 3.3 V
Output Voltage High (VOH)
1.4
V
IOH = 1 mA, (Pin 37) = 1.8 V
Output Voltage Low (VOL)
0.4
V
IOL = 1 mA, (Pin 37) = 1.8 V
TOTAL POWER DISSIPATION
All Blocks Running4
1060
1310
mW
Worst case over supply, temperature, process
Power-Down Mode
24
70
mW
Using either the power-down and enable
register (Register 0x0010) or the PWRDOWN pin
Digital Power-Down Mode
565
713
mW
Default with SYSCLK PLL Enabled
955
mW
After reset or power-up with fS = 1 GHz,
S4 = 0, S1 to S3 = 1, fSYSCLK = 25 MHz
Default with SYSCLK PLL Disabled
945
1115
mW
After reset or power-up with fS = 1 GHz,
S1 to S4 = 1
With REFA or REFB Power-Down
1105
mW
One reference still powered up
With HSTL Clock Driver Power-Down
1095
mW
With CMOS Clock Driver Power-Down
1107
mW
1 Must be
≤0 V relative to AVDD3 (Pin 14) and ≥0 V relative to AVSS (Pin 33, Pin 43).
2 Relative to AVSS (Pin 33, Pin 43).
3 Must be
≤0 V relative to AVDD (Pin 36) and ≥0 V relative to AVSS (Pin 33, Pin 43).
4 Typical measurement done with only REFA and HSTL output doubler turned off.
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