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參數(shù)資料
| 型號： | AD9549ABCPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 18/76頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN/SYNCHRONIZR 64LFCSP |
| 產(chǎn)品變化通告： | AD9549A Mask Change 22/Oct/2010 |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 類型： | 時鐘/頻率發(fā)生器，同步器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，Stratum |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，HSTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 750MHz |
| 電源電壓： | 1.71 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 帶卷 (TR) |
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AD9549
Rev. D | Page 25 of 76
The phase lock detect signal is generated once the control logic
observes that the output of the comparator has been in the true
Filter section for a description of the P-divider). When the phase
lock detect signal is asserted, it remains asserted until cleared
by an unlock event or by a device reset.
The duration of the lock detection process is programmable via
the phase lock watchdog timer bits. The interval is controlled by a
5-bit number, X (0 ≤ X ≤ 20).The absolute duration of the
phase lock detect interval is
S
X
LOCK
f
P
t
2
=
Hysteresis in the phase lock detection process is controlled by
specifying the minimum duration that qualifies as an unlock
event. An unlock event is declared when the control logic
observes that the output of the comparator has been in the false
state for 2Y + 1 periods of the P-divider clock (provided that the
phase lock detect signal has been asserted). Detection of an
unlock event clears the phase lock detect signal, and the phase
lock detection process is automatically restarted.
The time required to declare an unlock event is programmable
via the phase unlock watchdog timer bits. The interval is
controlled by a 3-bit number, Y (0 ≤ Y ≤ 7). The absolute
duration of the unlock detection interval is
S
Y
UNLOCK
f
P
t
1
2
+
=
Figure 31 shows the basic timing relationship between the
reference signal at the input to the phase detector, the phase
error magnitude, the output of the comparator, and the output
of the phase lock detector. The example shown here assumes
that X = 3 and Y = 1.
Note that the phase and frequency lock detectors may erroneously
indicate phase/frequency lock while in holdover. Therefore, the
user should use the phase and frequency lock signals in conjunc-
tion with either the reference input valid or the holdover active
signals to indicate phase/frequency lock.
Frequency Lock Detection
Frequency lock detection is similar to phase lock detection, with
the exception that the difference between successive phase
samples is the source of information. A running difference of
the phase samples serves as a digital approximation to the time-
derivative of the phase samples, which is analogous to frequency.
The formula for the frequency lock detect threshold value
(FLDT) is
×
=
2
7
10
_
10
2
round
R
f
R
Gain
FPFD
f
FLDT
where fR is the frequency of the active reference, R is the value of
the reference prescaler, and Δf is the maximum frequency
deviation of fR that is considered to indicate a frequency-locked
condition (Δf ≥ 0).
06744-
031
ABSOLUTE
VALUE
DIFFERENCER
DIGITAL
COMPARATOR
CONTROL LOGIC
UNLOCK
TIMER
LOCK
TIMER
FREQUENCY LOCK DETECT
THRESHOLD
Y
X
CLOSE
LOOP
FREQUENCY
LOCK
DETECT
RESET
P-DIVIDER
CLOCK
PHASE
DETECTOR
SAMPLES
I/O
REGISTERS
3
5
Figure 30. Frequency Lock Detection
06744-
030
fR/R
fS/P
0
THRESHOLD
COMPARATOR
PHASE ERROR
MAGNITUDE
SAMPLES
LOCK
TIMER
(X = 3)
UNLOCK
TIMER
(Y = 1)
8
4
LOCKED
THRESHOLD
Figure 31. Lock/Unlock Detection Timing
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