fVCXO = 122.88 MHz single ended," />
參數(shù)資料
型號(hào)： AD9523/PCBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 34/60頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD9523
設(shè)計(jì)資源： AD9523(-1) Eval Board Schematic
AD9523(-1) BOM
AD9523(-1) Gerber Files
標(biāo)準(zhǔn)包裝： 1
主要目的： 計(jì)時(shí)，時(shí)鐘發(fā)生器
嵌入式： 否
已用 IC / 零件： AD9523
主要屬性： 板載 PLL 環(huán)路濾波器
次要屬性： LED 狀態(tài)指示器
已供物品： 板
相關(guān)產(chǎn)品： AD9523BCPZ-REEL7-ND - IC INTEGER-N CLCK GEN 72LFCSP
AD9523BCPZ-ND - IC INTEGER-N CLCK GEN 72LFCSP
AD9523-1BCPZ-ND - IC INTEGER-N CLCK GEN 72LFCSP
AD9523-1BCPZ-REEL7-ND - IC INTEGER-N CLCK GEN 72LFCSP
AD9523
Data Sheet
Rev. C | Page 4 of 60
SPECIFICATIONS
fVCXO = 122.88 MHz single ended, REFA and REFB on differential at 30.72 MHz, fVCO = 3932.16 MHz, doubler is off, channel control low
power mode off, divider phase =1, unless otherwise noted. Typical is given for VDD = 3.3 V ± 5%, and TA = 25°C, unless otherwise
noted. Minimum and maximum values are given over the full VDD, and TA (40°C to +85°C) variation, as listed in Table 1.
CONDITIONS
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
SUPPLY VOLTAGE
VDD3_PLL1, Supply Voltage for PLL1
3.3
V
3.3 V ± 5%
VDD3_PLL2, Supply Voltage for PLL2
3.3
V
3.3 V ± 5%
VDD3_REF, Supply Voltage Clock Output Drivers Reference
3.3
V
3.3 V ± 5%
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
3.3
V
3.3 V ± 5%
VDD1.8_OUT[x:y],1 Supply Voltage Clock Dividers
1.8
V
1.8 V ± 5%
TEMPERATURE
Ambient Temperature Range, TA
40
+25
+85
°C
Junction Temperature, TJ
115
°C
1 x and y are the pair of differential outputs that share the same power supply. For example, VDD3_OUT[0:1] is Supply Voltage Clock Output OUT0, OUT0 (Pin 68 and Pin 67,
respectively) and Supply Voltage Clock Output OUT1, OUT1 (Pin 65 and Pin 64, respectively).
SUPPLY CURRENT
Table 2.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
SUPPLIES OTHER THAN CLOCK OUTPUT DRIVERS
VDD3_PLL1, Supply Voltage for PLL1
37
43
mA
Decreases by 9 mA typical if REFB is turned off
VDD3_PLL2, Supply Voltage for PLL2
67
77.7
mA
VDD3_REF, Supply Voltage Clock Output Drivers Reference
LVPECL Mode
5
6
mA
Only one output driver turned on; for each
additional output that is turned on, the
current increments by 1.2 mA maximum
LVDS Mode
4
4.8
mA
Only one output driver turned on; for each
additional output that is turned on, the
current increments by 1.2 mA maximum
HSTL Mode
3
3.6
mA
Values are independent of the number of
outputs turned on
CMOS Mode
3
3.6
mA
Values are independent of the number of
outputs turned on
VDD1.8_OUT[x:y],1 Supply Voltage Clock Dividers2
3.5
4.2
mA
Current for each divider: f = 245.76 MHz
CLOCK OUTPUT DRIVERS
LVDS Mode, 7 mA
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
16
17.4
mA
f = 61.44 MHz
LVDS Mode, 3.5 mA
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
5
6.2
mA
f = 245.76 MHz
LVPECL Mode
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
17
18.9
mA
f = 122.88 MHz
HSTL Mode, 16 mA
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
21
24.0
mA
f = 122.88 MHz
HSTL Mode, 8 mA
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
14
16.3
mA
f = 122.88 MHz
CMOS Mode (Single-Ended)
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
2
2.4
mA
f = 15.36 MHz, 10 pF Load
1 x and y are the pair of differential outputs that share the same power supply. For example, VDD3_OUT[0:1] is Supply Voltage Clock Output OUT0, OUT0 (Pin 68 and Pin 67,
respectively) and Supply Voltage Clock Output OUT1, OUT1 (Pin 65 and Pin 64, respectively).
2 The current for Pin 63 (VDD1_OUT[0:3]) is 2× that of the other VDD11.8_OUT[x:y] pairs.
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