參數(shù)資料
型號(hào)： AD9523/PCBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 25/60頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD9523
設(shè)計(jì)資源： AD9523(-1) Eval Board Schematic
AD9523(-1) BOM
AD9523(-1) Gerber Files
標(biāo)準(zhǔn)包裝： 1
主要目的： 計(jì)時(shí)，時(shí)鐘發(fā)生器
嵌入式： 否
已用 IC / 零件： AD9523
主要屬性： 板載 PLL 環(huán)路濾波器
次要屬性： LED 狀態(tài)指示器
已供物品： 板
相關(guān)產(chǎn)品： AD9523BCPZ-REEL7-ND - IC INTEGER-N CLCK GEN 72LFCSP
AD9523BCPZ-ND - IC INTEGER-N CLCK GEN 72LFCSP
AD9523-1BCPZ-ND - IC INTEGER-N CLCK GEN 72LFCSP
AD9523-1BCPZ-REEL7-ND - IC INTEGER-N CLCK GEN 72LFCSP
Data Sheet
AD9523
Rev. C | Page 31 of 60
SPI SERIAL PORT OPERATION
Pin Descriptions
SCLK (serial clock) is the serial shift clock. This pin is an input.
SCLK is used to synchronize serial control port reads and writes.
Write data bits are registered on the rising edge of this clock,
and read data bits are registered on the falling edge. This pin is
internally pulled down by a 40 k resistor to ground.
SDIO (serial data input/output) is a dual-purpose pin and acts
either as an input only (unidirectional mode) or as an input/
output (bidirectional mode). The AD9523 defaults to the
bidirectional I/O mode.
SDO (serial data out) is used only in the unidirectional I/O
mode as a separate output pin for reading back data.
CS (chip select bar) is an active low control that gates the read
and write cycles. When CS is high, the SDO and SDIO pins
enter a high impedance state. This pin is internally pulled up by
a 40 k resistor to VDD3_REF.
AD9523
SERIAL
CONTROL
PORT
CS
SCLK/SCL
SDIO/SDA
SDO
08439-
034
Figure 36. Serial Control Port
SPI Mode Operation
In SPI mode, single or multiple byte transfers are supported,
as well as MSB first or LSB first transfer formats. The AD9523
serial control port can be configured for a single bidirectional
I/O pin (SDIO only) or for two unidirectional I/O pins (SDIO/
SDO). By default, the AD9523 is in bidirectional mode. Short
instruction mode (8-bit instructions) is not supported. Only
long (16-bit) instruction mode is supported.
A write or a read operation to the AD9523 is initiated by pulling
CS low.
The CS stalled high mode is supported in data transfers where
three or fewer bytes of data (plus instruction data) are transferred
(see Table 25). In this mode, the CS pin can temporarily return
high on any byte boundary, allowing time for the system controller
to process the next byte. CS can go high only on byte boundaries;
however, it can go high during either phase (instruction or data)
of the transfer.
During this period, the serial control port state machine enters
a wait state until all data is sent. If the system controller decides
to abort the transfer before all of the data is sent, the state machine
must be reset either by completing the remaining transfers or by
returning CS low for at least one complete SCLK cycle (but fewer
than eight SCLK cycles). Raising the CS pin on a nonbyte
boundary terminates the serial transfer and flushes the buffer.
In streaming mode (see Table 25), any number of data bytes can
be transferred in a continuous stream. The register address is
automatically incremented or decremented (see the SPI MSB/LSB
First Transfers section). CS must be raised at the end of the last
byte to be transferred, thereby ending streaming mode.
Communication Cycle—Instruction Plus Data
There are two parts to a communication cycle with the AD9523.
The first part writes a 16-bit instruction word into the AD9523,
coincident with the first 16 SCLK rising edges. The instruction
word provides the AD9523 serial control port with information
regarding the data transfer, which is the second part of the
communication cycle. The instruction word defines whether
the upcoming data transfer is a read or a write, the number of
bytes in the data transfer, and the starting register address for
the first byte of the data transfer.
Write
If the instruction word is for a write operation, the second part
is the transfer of data into the serial control port buffer of the
AD9523. Data bits are registered on the rising edge of SCLK.
The length of the transfer (one, two, or three bytes or streaming
mode) is indicated by two bits (W1, W0) in the instruction byte.
When the transfer is one, two, or three bytes but not streaming, CS
can be raised after each sequence of eight bits to stall the bus
(except after the last byte, where it ends the cycle). When the bus
is stalled, the serial transfer resumes when CS is lowered. Raising
the CS pin on a nonbyte boundary resets the serial control port.
During a write, streaming mode does not skip over reserved or
blank registers, and the user can write 0x00 to the reserved
register addresses.
Because data is written into a serial control port buffer area, and
not directly into the actual control registers of the AD9523, an
additional operation is needed to transfer the serial control port
buffer contents to the actual control registers of the AD9523,
thereby causing them to become active. The update registers
operation consists of setting the self-clearing IO_Update bit,
Bit 0 of Register 0x234 (see Table 57). Any number of data bytes
can be changed before executing an update registers operation.
The update registers simultaneously actuates all register changes
that have been written to the buffer since any previous update.
Read
The AD9523 supports only the long instruction mode. If the
instruction word is for a read operation, the next N × 8 SCLK
cycles clock out the data from the address specified in the
instruction word, where N is 1 to 3 as determined by Bits[W1:W0].
If N = 4, the read operation is in streaming mode, continuing
until CS is raised. During an SPI read, serial data on SDIO (or
SDO in the case of 4-wire mode) transitions on the SCLK falling
edge, and is normally sampled on the SCLK rising edge. To read
the last bit correctly, the SPI host must be able to tolerate a zero
hold time. In cases where zero hold time is not possible, the user
can either use streaming mode and delay the rising edge of CS, or
sample the serial data on the SCLK falling edge. However, to
sample the data correctly on the SCLK falling edge, the user
must ensure that the setup time is greater than tDV (time data
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