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參數(shù)資料
| 型號： | AD9523/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 18/60頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD9523 |
| 設計資源： | AD9523(-1) Eval Board Schematic AD9523(-1) BOM AD9523(-1) Gerber Files |
| 標準包裝： | 1 |
| 主要目的： | 計時，時鐘發(fā)生器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9523 |
| 主要屬性： | 板載 PLL 環(huán)路濾波器 |
| 次要屬性： | LED 狀態(tài)指示器 |
| 已供物品： | 板 |
| 相關產(chǎn)品： | AD9523BCPZ-REEL7-ND - IC INTEGER-N CLCK GEN 72LFCSP AD9523BCPZ-ND - IC INTEGER-N CLCK GEN 72LFCSP AD9523-1BCPZ-ND - IC INTEGER-N CLCK GEN 72LFCSP AD9523-1BCPZ-REEL7-ND - IC INTEGER-N CLCK GEN 72LFCSP |
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Data Sheet
AD9523
Rev. C | Page 25 of 60
When using the sync dividers bit, the user first sets and then
clears the bit. The synchronization event is the clearing
operation (that is, the Logic 1 to Logic 0 transition of the bit).
The dividers are all automatically synchronized to each other
when PLL2 is ready. The dividers support programmable phase
offsets from 0 to 63 steps, in half periods of the input clock (for
example, the VCO divider output clock). The phase offsets are
incorporated in the dividers through a preset for the first output
clock period of each divider. Phase offsets are sup-ported only by
programming the initial phase and divide value and then issuing a
sync to the distribution (automatically at startup or manually, if
desired).
When using the SYNC pin (Pin 17), there are 11 VCO divider
output pipe line delays plus one period of the clock from the
rising edge of SYNC to the clock output. There is at least one
extra VCO divider period of uncertainty because the SYNC
signal and the VCO divider output are asynchronous.
In normal operation, the phase offsets are already programmed
through the EEPROM or the SPI/I2C port before the AD9523
starts to provide outputs. Although the user cannot adjust the
phase offsets while the dividers are operating, it is possible to
adjust the phase of all the outputs together without powering
down PLL1 and PLL2. This is accomplished by programming
the new phase offset, using Bits[7:2] in Register 0x192 (see
Table 51) and then issuing a divide sync signal by using the
SYNC pin or the sync dividers bit (Register 0x232, Bit 0). All
outputs that are not programmed to ignore the sync are disabled
temporarily while the sync is active. Note that, if an output is used
for the zero delay path, it also disappears momentarily. However,
this is desirable because it ensures that all the synchronized outputs
have a deterministic phase relationship with respect to the zero
delay output and, therefore, also with respect to the input.
FAN OUT
VCO OUTPUT DIVIDER
SYNC (PIN 17)
SYNC
SYNC DIVIDERS BIT
08439-
02
5
DIVIDER
DRIVER
OUTx
OUT
SYNC
PHASE
DIVIDE
Figure 27. Clock Output Synchronization Block Diagram
DIVIDE = 2, PHASE = 0
DIVIDE = 2, PHASE = 6
VCO DIVIDER OUTPUT CLOCK
SYNC
CONTROL
6 × 0.5 PERIODS
0
843
9-
026
Figure 28. Clock Output Synchronization Timing Diagram
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