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參數(shù)資料
| 型號： | AD9523-1BCPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 42/60頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC INTEGER-N CLCK GEN 72LFCSP |
| 標(biāo)準包裝： | 400 |
| 類型： | 時鐘/頻率發(fā)生器，扇出緩沖器（分配），多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，光纖通道，SONET/SDH |
| 輸入： | CMOS |
| 輸出： | HSTL，LVCMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:14 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 1GHz |
| 電源電壓： | 1.768 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 72-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 72-LFCSP |
| 包裝： | 帶卷 (TR) |
| 配用： | AD9523/PCBZ-ND - BOARD EVAL FOR AD9523 |
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AD9523-1
Rev. B | Page 47 of 60
Table 40. PLL1 Input Receiver Control
Address
Bits
Bit Name
Description
7
REF_TEST input receiver enable
1: enabled.
0: disabled (default).
6
REFB differential receiver enable
1: differential receiver mode.
0: single-ended receiver mode (also depends on Register 0x01B, Bit 1) (default).
5
REFA differential receiver enable
1: differential receiver mode.
0: single-ended receiver mode (also depends on Register 0x01B, Bit 0) (default).
4
REFB receiver enable
REFB receiver power-down control mode only when Bit 2 = 1.
1: enable REFB receiver.
0: power-down (default).
3
REFA receiver enable
REFA receiver power-down control mode only when Bit 2 = 1.
1: enable REFA receiver.
0: power-down (default).
2
Input REFA and REFB receiver
power-down control enable
Enables control over power-down of the input receivers, REFA and REFB.
1: power-down control enabled.
0: both receivers enabled (default).
1
OSC_IN single-ended receiver
mode enable (CMOS mode)
Selects which single-ended input pin is enabled when in the single-ended receiver
mode (Register 0x01A, Bit 0 = 0).
1: negative receiver from oscillator input (OSC_IN pin) selected.
0: positive receiver from oscillator input (OSC_IN pin) selected (default).
0x01A
0
OSC_IN differential receiver mode
enable
1: differential receiver mode.
0: single-ended receiver mode (also depends on Bit 1) (default).
Table 41. REF_TEST, REFA, REFB, and ZD_IN Control
Address
Bits
Bit Name
Description
7
Bypass REF_TEST divider
Puts the divider into bypass mode (same as programming the divider word to 0 or 1).
1: divider in bypass mode (divide = 1).
0: divider normal operation.
6
Bypass feedback divider
Puts the divider into bypass mode (same as programming the divider word to 0 or 1).
1: divider in bypass mode (divide = 1).
0: divider normal operation.
5
Zero delay mode
Selects the zero delay mode used (via the ZD_IN pin) when Register 0x01B, Bit 4 = 0.
Otherwise, this bit is ignored.
1: internal zero delay mode. The zero delay receiver is powered down. The internal
zero delay path from Distribution Divider Channel 0 is used.
0: external zero delay mode. The ZD_IN receiver is enabled.
4
OSC_IN signal feedback for PLL1
Controls the input PLL feedback path, local feedback from the OSC_IN receiver or
zero delay mode.
1: OSC_IN receiver input used for the input PLL feedback (non-zero delay mode).
0: zero delay mode enabled (also depends on Register 0x01B, Bit 4 to select the
zero delay path.
3
ZD_IN single-ended receiver
mode enable (CMOS mode)
Selects which single-ended input pin is enabled when in the single-ended receiver
mode (Register 0x01B, Bit 2 = 0).
1: ZD_IN pin enabled.
0: ZD_IN pin enabled.
2
ZD_IN differential receiver mode
enable
1: differential receiver mode.
0: single-ended receiver mode (also depends on Register 0x01B, Bit 3).
1
REFB single-ended receiver mode
enable (CMOS mode)
Selects which single-ended input pin is enabled when in single-ended receiver mode
(Register 0x01A, Bit 6 = 0).
1: REFB pin enabled.
0: REFB pin enabled.
0x01B
0
REFA single-ended receiver mode
enable (CMOS mode)
Selects which single-ended input pin is enabled when in single-ended receiver mode
(Register 0x01A, Bit 5 = 0).
1: REFA pin enabled.
0: REFA pin enabled.
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