參數(shù)資料
型號(hào): AD9523-1BCPZ-REEL7
廠商: Analog Devices Inc
文件頁數(shù): 24/60頁
文件大?。?/td> 0K
描述: IC INTEGER-N CLCK GEN 72LFCSP
標(biāo)準(zhǔn)包裝: 400
類型: 時(shí)鐘/頻率發(fā)生器,扇出緩沖器(分配),多路復(fù)用器
PLL:
主要目的: 以太網(wǎng),光纖通道,SONET/SDH
輸入: CMOS
輸出: HSTL,LVCMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 2:14
差分 - 輸入:輸出: 是/是
頻率 - 最大: 1GHz
電源電壓: 1.768 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 72-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 72-LFCSP
包裝: 帶卷 (TR)
配用: AD9523/PCBZ-ND - BOARD EVAL FOR AD9523
AD9523-1
Rev. B | Page 30 of 60
A repeated start (Sr) condition can be used in place of a stop
condition. Furthermore, a start or stop condition can occur at
any time; partially transferred bytes are discarded.
For an I2C data write transfer containing multiple data bytes,
the peripheral drives a no acknowledge for the data byte that
follows a write to Register 0x234, thereby ending the I2C transfer.
For an I2C data read transfer containing multiple data bytes,
the peripheral drives data bytes of 0x00 for subsequent reads that
follow a read from Register 0x234.
Data Transfer Format
Send byte format. The send byte protocol is used to set up the register address for subsequent commands.
S
Slave Address
W
A
RAM Address High Byte
A
RAM Address Low Byte
A
P
Write byte format. The write byte protocol is used to write a register address to the RAM, starting from the specified RAM address.
S
Slave Address
W
A
RAM Address
High Byte
A
RAM Address
Low Byte
A
RAM
Data 0
A
RAM
Data 1
A
RAM
Data 2
A
P
Receive byte format. The receive byte protocol is used to read the data byte(s) from the RAM, starting from the current address.
S
Slave Address
R
A
RAM Data 0
A
RAM Data 1
A
RAM Data 2
A
P
Read byte format. The combined format of the send byte and the receive byte.
S
Slave
Address
W
A
RAM Address
High Byte
A
RAM Address
Low Byte
A
Sr
Slave
Address
R
A
RAM
Data 0
A
RAM
Data 1
A
RAM
Data 2
A
P
IC Serial Port Timing
SDA
SCL
S
Sr
P
S
tFALL
tSET; DAT
tLOW
tRISE
tHLD; STR
tHLD; DAT
tHIGH
tFALL
tSET; STR
tHLD; STR
tSPIKE
tSET; STP
tRISE
tIDLE
09278
-1
65
Figure 37. IC Serial Port Timing
Table 23. I2C Timing Definitions
Parameter
Description
fI2C
IC clock frequency
tIDLE
Bus idle time between stop and start conditions
tHLD; STR
Hold time for repeated start condition
tSET; STR
Setup time for repeated start condition
tSET; STP
Setup time for stop condition
tHLD; DAT
Hold time for data
tSET; DAT
Setup time for data
tLOW
Duration of SCL clock low
tHIGH
Duration of SCL clock high
tRISE
SCL/SDA rise time
tFALL
SCL/SDA fall time
tSPIKE
Voltage spike pulse width that must be suppressed by the input filter
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