參數(shù)資料
型號(hào): AD9523-1BCPZ-REEL7
廠商: Analog Devices Inc
文件頁(yè)數(shù): 37/60頁(yè)
文件大小: 0K
描述: IC INTEGER-N CLCK GEN 72LFCSP
標(biāo)準(zhǔn)包裝: 400
類型: 時(shí)鐘/頻率發(fā)生器,扇出緩沖器(分配),多路復(fù)用器
PLL:
主要目的: 以太網(wǎng),光纖通道,SONET/SDH
輸入: CMOS
輸出: HSTL,LVCMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 2:14
差分 - 輸入:輸出: 是/是
頻率 - 最大: 1GHz
電源電壓: 1.768 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 72-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 72-LFCSP
包裝: 帶卷 (TR)
配用: AD9523/PCBZ-ND - BOARD EVAL FOR AD9523
AD9523-1
Rev. B | Page 42 of 60
Addr
(Hex)
Register
Name
(MSB)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
(LSB)
Bit 0
Default
Value
(Hex)
0x1A2
Channel 6
control
Invert
divider
output
Ignore
sync
Power
down
channel
Lower power
mode
Driver mode
0x00
0x1A3
10-bit channel divider[7:0] (LSB)
0x1F
0x1A4
Divider phase[5:0]
10-bit channel divider[9:8] (MSB)
0x04
0x1A5
Channel 7
control
Invert
divider
output
Ignore
sync
Power
down
channel
Lower power
mode
Driver mode
0x20
0x1A6
10-bit channel divider[7:0] (LSB)
0x1F
0x1A7
Divider phase[5:0]
10-bit channel divider[9:8] (MSB)
0x04
0x1A8
Channel 8
control
Invert
divider
output
Ignore
sync
Power
down
channel
Lower power
mode
Driver mode
0x00
0x1A9
10-bit channel divider[7:0] (LSB)
0x1F
0x1AA
Divider phase[5:0]
10-bit channel divider[9:8] (MSB)
0x04
0x1AB
Channel 9
control
Invert
divider
output
Ignore
sync
Power
down
channel
Lower power
mode
Driver mode
0x20
0x1AC
10-bit channel divider[7:0] (LSB)
0x1F
0x1AD
Divider phase[5:0]
10-bit channel divider[9:8] (MSB)
0x04
0x1AE
Channel 10
control
Invert
divider
output
Ignore
sync
Power
down
channel
Lower power
mode
Driver mode
0x00
0x1AF
10-bit channel divider[7:0] (LSB)
0x1F
0x1B0
Divider phase[5:0]
10-bit channel divider[9:8] (MSB)
0x04
0x1B1
Channel 11
control
Invert
divider
output
Ignore
sync
Power
down
channel
Lower power
mode
Driver mode
0x20
0x1B2
10-bit channel divider[7:0] (LSB)
0x1F
0x1B3
Divider phase[5:0]
10-bit channel divider[9:8] (MSB)
0x04
0x1B4
Channel 12
control
Invert
divider
output
Ignore
sync
Power
down
channel
Lower power
mode
Driver mode
0x00
0x1B5
10-bit channel divider[7:0] (LSB)
0x1F
0x1B6
Divider phase[5:0]
10-bit channel divider[9:8] (MSB)
0x04
0x1B7
Channel 13
control
Invert
divider
output
Ignore
sync
Power
down
channel
Lower power
mode
Driver mode
0x20
0x1B8
10-bit channel divider[7:0] (LSB)
0x1F
0x1B9
Divider phase[5:0]
10-bit channel divider[9:8] (MSB)
0x04
0x1BA
PLL1 output
control
CLK2 select[2:0]
PLL1 output
CMOS driver
strength
Out PLL1 output
0x00
0x1BB
PLL1 output
channel
control
PLL1
output
driver
power-
down
CLK2 select[5:3]
Reserved
Route
VCXO
clock to
Ch 3
divider
input
Route
VCXO
clock to
Ch 2
divider
input
Route VCXO
clock to Ch 1
divider input
Route VCXO
clock to Ch 0
divider input
0x80
Readback
0x22C
Readback 0
Status
PLL2
reference
clock
Status
PLL2
feedback
clock
Status
VCXO
Status
REF_TEST
Status
REFB
Status
REFA
Lock detect
PLL2
Lock detect
PLL1
0x22D
Readback 1
Reserved
Holdover
active
Selected
reference
(in auto
mode)
Reserved
VCO
calibration
in progress
0x22E
Readback 2
Reserved
0x22F
Readback 3
Reserved
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