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參數(shù)資料
| 型號(hào)： | AD9523-1BCPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 26/60頁 |
| 文件大小： | 0K |
| 描述： | IC INTEGER-N CLCK GEN 72LFCSP |
| 標(biāo)準(zhǔn)包裝： | 400 |
| 類型： | 時(shí)鐘/頻率發(fā)生器，扇出緩沖器（分配），多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，光纖通道，SONET/SDH |
| 輸入： | CMOS |
| 輸出： | HSTL，LVCMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:14 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 1GHz |
| 電源電壓： | 1.768 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 72-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 72-LFCSP |
| 包裝： | 帶卷 (TR) |
| 配用： | AD9523/PCBZ-ND - BOARD EVAL FOR AD9523 |
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AD9523-1
Rev. B | Page 32 of 60
The default mode of the AD9523-1 serial control port is the
bidirectional mode. In bidirectional mode, both the sent data
and the readback data appear on the SDIO pin. It is also possible
to set the AD9523-1 to unidirectional mode. In unidirectional
mode, the readback data appears on the SDO pin.
The AD9523-1 instruction word and byte data can be MSB first
or LSB first. Any data written to Register 0x000 must be mirrored:
Bit 7 is mirrored to Bit 0, Bit 6 to Bit 1, Bit 5 to Bit 2, and Bit 4 to
Bit 3. This makes it irrelevant whether LSB first or MSB first is
in effect. The default for the AD9523-1 is MSB first.
A readback request reads the data that is in the serial control port
buffer area or the data that is in the active registers (see Figure 39).
When LSB first is set by Register 0x000, Bit 1, and Register 0x000,
Bit 6, it takes effect immediately because it affects only the
operation of the serial control port and does not require that an
update be executed.
SERIAL
CONTROL
PORT
BUFFER
REGISTERS
UPDATE
REGISTERS
ACTIVE
REGISTERS
SCLK/SCL
SDO
SDIO/SDA
CS
092
78-
03
5
When MSB first mode is active, the instruction and data bytes
must be written from MSB to LSB. Multibyte data transfers in
MSB first format start with an instruction byte that includes the
register address of the most significant data byte. Subsequent
data bytes must follow in order from the high address to the
low address. In MSB first mode, the serial control port internal
address generator decrements for each data byte of the multibyte
transfer cycle.
Figure 39. Relationship Between Serial Control Port Buffer Registers and
Active Registers
SPI INSTRUCTION WORD (16 BITS)
When LSB first mode is active, the instruction and data bytes
must be written from LSB to MSB. Multibyte data transfers in
LSB first format start with an instruction byte that includes the
register address of the least significant data byte, followed by
multiple data bytes. In a multibyte transfer cycle, the internal
byte address generator of the serial port increments for each byte.
The MSB of the instruction word is R/W, which indicates
whether the instruction is a read or a write. The next two bits
([W1:W0]) indicate the length of the transfer in bytes. The final
13 bits are the address ([A12:A0]) at which to begin the read or
write operation.
For a write, the instruction word is followed by the number of
bytes of data indicated by Bits[W1:W0] (see Table 24).
Table 24. Byte Transfer Count
W1
The AD9523-1 serial control port register address decrements
from the register address just written toward 0x000 for multibyte
I/O operations if the MSB first mode is active (default). If the
LSB first mode is active, the register address of the serial control
port increments from the address just written toward 0x234 for
multibyte I/O operations. Unused addresses are not skipped for
these operations.
W0
Bytes to Transfer
0
1
0
1
2
1
0
3
1
Streaming mode
For multibyte accesses that cross Address 0x234 or Address 0x000
in MSB first mode, the SPI internally disables writes to subsequent
registers and returns zeros for reads to subsequent registers.
Bits[A12:A0] select the address within the register map that is
written to or read from during the data transfer portion of the
communications cycle. Only Bits[A11:A0] are needed to cover
the range of the 0x234 registers used by the AD9523-1. Bit A12
must always be 0. For multibyte transfers, this address is the
starting byte address. In MSB first mode, subsequent bytes
decrement the address.
Streaming mode always terminates when crossing address
boundaries (as shown in Table 25).
Table 25. Streaming Mode (No Addresses Are Skipped)
Write Mode
Address Direction
Stop Sequence
MSB First
Decrement
…, 0x001, 0x000, stop
Table 26. Serial Control Port, 16-Bit Instruction Word, MSB First
MSB
LSB
I15
I14
I13
I12
I11
I10
I9
I8
I7
I6
I5
I4
I3
I2
I1
I0
R/W
W1
W0
A12 = 0
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
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| AD9523BCPZ | 功能描述:IC INTEGER-N CLCK GEN 72LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時(shí)鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時(shí)鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| AD9523BCPZ-REEL7 | 功能描述:IC INTEGER-N CLCK GEN 72LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時(shí)鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時(shí)鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| AD9524 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Jitter Cleaner and Clock Generator with 6 Differential or 13 LVCMOS Outputs |
| AD9524/PCBZ | 功能描述:BOARD EVAL FOR AD9524 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| AD9524BCPZ | 功能描述:IC INTEGER-N CLCK GEN 48LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時(shí)鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時(shí)鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
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