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參數(shù)資料
| 型號(hào)： | AD9523-1BCPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 25/60頁 |
| 文件大小： | 0K |
| 描述： | IC INTEGER-N CLCK GEN 72LFCSP |
| 標(biāo)準(zhǔn)包裝： | 400 |
| 類型： | 時(shí)鐘/頻率發(fā)生器，扇出緩沖器（分配），多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，光纖通道，SONET/SDH |
| 輸入： | CMOS |
| 輸出： | HSTL，LVCMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:14 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 1GHz |
| 電源電壓： | 1.768 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 72-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 72-LFCSP |
| 包裝： | 帶卷 (TR) |
| 配用： | AD9523/PCBZ-ND - BOARD EVAL FOR AD9523 |
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AD9523-1
Rev. B | Page 31 of 60
SPI SERIAL PORT OPERATION
Pin Descriptions
SCLK (serial clock) is the serial shift clock. This pin is an input.
SCLK is used to synchronize serial control port reads and writes.
Write data bits are registered on the rising edge of this clock,
and read data bits are registered on the falling edge. This pin is
internally pulled down by a 40 kΩ resistor to ground.
SDIO (serial data input/output) is a dual-purpose pin and acts
either as an input only (unidirectional mode) or as an input/
output (bidirectional mode). The AD9523-1 defaults to the
bidirectional I/O mode.
SDO (serial data out) is used only in the unidirectional I/O mode
as a separate output pin for reading back data. SDO is always
active; therefore, the unidirectional I/O mode should not be
used in a multislave environment.
CS (chip select bar) is an active low control that gates the read
and write cycles. When CS is high, SDIO is in a high impedance
state. This pin is internally pulled up by a 40 kΩ resistor to
VDD3_REF.
AD9523-1
SERIAL
CONTROL
PORT
CS
SCLK/SCL
SDIO/SDA
SDO
09
278
-0
34
Figure 38. Serial Control Port
SPI Mode Operation
In SPI mode, single or multiple byte transfers are supported,
as well as MSB first or LSB first transfer formats. The AD9523-1
serial control port can be configured for a single bidirectional
I/O pin (SDIO only) or for two unidirectional I/O pins (SDIO/
SDO). By default, the AD9523-1 is in bidirectional mode. Short
instruction mode (8-bit instructions) is not supported. Only
long (16-bit) instruction mode is supported.
A write or a read operation to the AD9523-1 is initiated by
pulling CS low.
The CS stalled high mode is supported in data transfers where
three or fewer bytes of data (plus instruction data) are transferred
(see
). In this mode, the
CS pin can temporarily return
high on any byte boundary, allowing time for the system controller
to process the next byte. CS can go high only on byte boundaries;
however, it can go high during either phase (instruction or data)
of the transfer.
During this period, the serial control port state machine enters
a wait state until all data is sent. If the system controller decides
to abort the transfer before all of the data is sent, the state machine
must be reset either by completing the remaining transfers or by
returning CS low for at least one complete SCLK cycle (but fewer
than eight SCLK cycles). Raising the CS pin on a nonbyte
boundary terminates the serial transfer and flushes the buffer.
In streaming mode (see Table 24), any number of data bytes can
be transferred in a continuous stream. The register address is
automatically incremented or decremented (see the SPI MSB/LSB
First Transfers section). CS must be raised at the end of the last
byte to be transferred, thereby ending streaming mode.
Communication Cycle—Instruction Plus Data
There are two parts to a communication cycle with the
AD9523-1. The first part writes a 16-bit instruction word into
the AD9523-1, coincident with the first 16 SCLK rising edges.
The instruction word provides the AD9523-1 serial control port
with information regarding the data transfer, which is the
second part of the communication cycle. The instruction word
defines whether the upcoming data transfer is a read or a write,
the number of bytes in the data transfer, and the starting
register address for the first byte of the data transfer.
Write
If the instruction word is for a write operation, the second part
is the transfer of data into the serial control port buffer of the
AD9523-1. Data bits are registered on the rising edge of SCLK.
The length of the transfer (one, two, or three bytes or streaming
mode) is indicated by two bits (W1, W0) in the instruction byte.
When the transfer is one, two, or three bytes but not streaming, CS
can be raised after each sequence of eight bits to stall the bus
(except after the last byte, where it ends the cycle). When the bus
is stalled, the serial transfer resumes when CS is lowered. Raising
the CS pin on a nonbyte boundary resets the serial control port.
During a write, streaming mode does not skip over reserved or
blank registers, and the user can write 0x00 to the reserved
register addresses.
Because data is written into a serial control port buffer area, and
not directly into the actual control registers of the AD9523-1, an
additional operation is needed to transfer the serial control port
buffer contents to the actual control registers of the AD9523-1,
thereby causing them to become active. The update registers
operation consists of setting the self-clearing IO_Update bit,
Bit 0 of Register 0x234 (see Table 57). Any number of data bytes
can be changed before executing an update registers operation.
The update registers simultaneously actuates all register changes
that have been written to the buffer since any previous update.
Read
The AD9523-1 supports only the long instruction mode. If the
instruction word is for a read operation, the next N × 8 SCLK
cycles clock out the data from the address specified in the
instruction word, where N is 1 to 3 as determined by Bits[W1:W0].
If N = 4, the read operation is in streaming mode, continuing
until CS is raised. Streaming mode does not skip over reserved
or blank registers. The readback data is valid on the falling
edge of SCLK.
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| AD9523BCPZ | 功能描述:IC INTEGER-N CLCK GEN 72LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時(shí)鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時(shí)鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| AD9523BCPZ-REEL7 | 功能描述:IC INTEGER-N CLCK GEN 72LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時(shí)鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時(shí)鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| AD9524 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Jitter Cleaner and Clock Generator with 6 Differential or 13 LVCMOS Outputs |
| AD9524/PCBZ | 功能描述:BOARD EVAL FOR AD9524 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| AD9524BCPZ | 功能描述:IC INTEGER-N CLCK GEN 48LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時(shí)鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時(shí)鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
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