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參數(shù)資料
| 型號： | AD776 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 16-Bit 100 kSPS Oversampling ADC(16位100kSPS過采樣A/D轉(zhuǎn)換器) |
| 中文描述： | 16位100 kSPS的采樣ADC的（16位100ksps的過采樣的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 257K |
| 代理商： | AD776 |
AD776
–8–
REV. A
In consideration of the dynamic characteristics of the analog
input, an external op amp is generally required to provide a low
impedance drive. Care should be taken with op amp selection;
even with modest loading conditions, most available op amps do
not meet the low distortion requirements necessary to match the
performance capabilities of the AD776. T he AD712 op amp is a
good choice for low noise and low distortion.
SINGLE -E NDE D INPUT CONFIGURAT IONS
T he differential input of the AD776 provides a choice of several
different input connections. Figure 7 shows a simple configura-
tion for a single-ended input. AIN– is nominally biased at +2.5 V
by resistively dividing the +5 V power supply (AV
DD
). Since the
analog input impedance is a function of the input clock rate,
determination of bias resistor values to achieve a particular bias
voltage will vary with clock rate and AV
DD
.
T he circuit shown in Figure 7 is a low cost, minimal component
solution, but may suffer from poor power supply rejection as
noise present on the power supply could be coupled directly into
the AIN– pin. An improved input circuit is shown in Figure 8,
when the offset voltage is derived from the AD680 voltage refer-
ence. T he AD680 has 40
μ
V/V line regulation which results in
only a 20
μ
V error due to 10% supply fluctuation. T his improves
power supply rejection of AIN– input to approximately 88 dB.
5
6
7
12
11
10
9
1
18
8
3
2
4
0.1μF
100μF
10μF
47k
FSI
CLKIN
47k
10μF
AIN+
AIN–
DV
DD
AV
DD
AGND
FSO
DOUT CLK
DOUT
FSEL SF
13
DGND
DOE
TO
PROCESSOR
+5V
V p-p
AD776
10
19
REFOUT
REFIN
20
100μF
Figure 7. Simple Single-Ended Input Circuit
3
2
0.0047
μ
F
47k
47
μ
F
AIN+
AIN–
+5V
V p-p
AD776
AD680
22
μ
F
100
0.1
μ
F
100
47
<2 x
Figure 8. Single-Ended Input Circuit for Improved PSRR
For optimal performance in single-ended input applications, the
circuit in Figure 9 may be used to convert the input to a differ-
ential signal.
V
2
19
AIN–
AIN+
AD776
3
REFOUT
1k
75
0.01
μ
F
4.99k
AD712
AD712
AD680
+5V
0.1
μ
F
20
REFIN
NC = NO CONNECT
100
μ
F
300
+
4.99k
(NPO)
0.01
μ
F
10
μ
F
+
+
10
μ
F
4.99k
50
4.99k
10
μ
F
50
Figure 9. Single-Ended Input to Differential Circuit
RE FE RE NCE INPUT
T he AD776 has an on-chip 0.4 V
DD
reference voltage circuit
which can be used to drive REFIN, as shown in Figure 10.
Alternately, an external voltage reference may be used to supply
the required 2 V. REFIN exhibits characteristics similar to the
Analog Input in that the input impedance is a function of the
clock rate. T his is illustrated in T able III. T he minimum refer-
ence impedance is equal to 10
12
/2.5 f
CLK
, where f
CLK
is the
input clock rate.
T able III. Reference Input Impedance
Reference
Input
Impedance
(k
min)
Input
Clock Rate
(MHz)
Output
Sample
Rate (kHz)
12.8
6.4
6.144
5.6448
100
50
48
44.1
31.3
62.5
65.1
70.9
19
20
100
μ
F
REFIN
REFOUT
AD776
Figure 10. Simple Reference Voltage Circuit
While the internal reference will be adequate for most applica-
tions, power supply rejection and overall regulation may be
improved through the use of an external reference. T he process
of selecting an external voltage reference should include consid-
eration of drive capability, initial error, noise, and drift charac-
teristics. A suitable choice would be the AD680 as shown in
Figure 11.
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