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參數(shù)資料
| 型號： | AD776 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 16-Bit 100 kSPS Oversampling ADC(16位100kSPS過采樣A/D轉(zhuǎn)換器) |
| 中文描述： | 16位100 kSPS的采樣ADC的（16位100ksps的過采樣的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 4/12頁 |
| 文件大小： | 257K |
| 代理商： | AD776 |
AD776
–4–
REV. A
AD776 PIN DE SCRIPT ION
Symbol
Pin Number
T ype
Name and Function
AGND
AIN+
AIN–
CLK IN
1
2
3
4
Analog Ground. Return current for analog front end. No internal connection to DGND.
Analog Signal Input. Noninverting terminal.
Analog Signal Input. Inverting terminal.
Clock In. T his T T L compatible input accepts clock frequencies in the range of
1.0 MHz–12.8 MHz, with the output sample rate of the AD776 equal to CLK IN
divided by 128 in FIR filter mode and 32 in comb filter mode.
Frame Sync Input. FSI is an optional control pin used to synchronize internal cir-
cuits and to start or reset the serial output data. If FSI is grounded, frame syncs will
be automatically generated internally. When FSI is brought HIGH, serial data is
presented at the output (DOUT —Pin 11). T he purpose of FSI is to control exter-
nally the phasing of the A/D conversion process. FSI should be a periodic signal
occurring every 16 DOUT CLK clock cycles in the 12-bit/400 kHz mode and every
32 DOUT CLK clock cycles in the 16-bit/100 kHz mode. When utilized, FSI must
be synchronized to CLK IN as defined in the timing specification (see Figure 17).
FSI allows multiple AD776s to be synchronized using a common frame sync source,
requiring a common CLK IN signal.
Filter Select. FSEL = “0” selects FIR output. FSEL = “1” selects comb filter output.
Serial Format. Selects output format of DOUT and FSO when FSEL = “0.” See
Figures 14b and 15b.
+5 V
±
10%. Digital Power Supply.
Frame Sync Output. Indicates beginning of serial data transmission on DOUT . See
T iming Diagrams.
Serial Data Clock. See Figures 14a and 14b. In the FIR filter output mode
(FSEL = 0), DOUT CLK is CLK IN divided by four; in the comb filter output mode
(FSEL = 1), DOUT CLK is CLK IN divided by two.
Data Output. Serial data is transmitted MSB first, twos complement format, once
per FSO cycle with the data synchronous with DOUT CLK .
Data Output Enable. Serial data (Pin 11) is an active output when
DOE
= “0.”
Serial data is three stated when
DOE
= “1.”
Digital Ground. Return current for digital circuitry and pad drivers.
T est Points. T hese pins must be connected to DGND.
+5 V
±
10%. Analog Power Supply.
Internal Reference Output. Nominally +2 V with AV
DD
= +5.0 V.
Reference Input. +2 V maximum.
I
I
I
FSI
5
I
FSEL
SF
6
7
I
I
DV
DD
FSO
8
9
O
DOUT CLK
10
O
DOUT
11
O
DOE
12
I
DGND
T P3, T P2, T P1, T P0
AV
DD
REFOUT
REFIN
13
14, 15, 16, 17
18
19
20
O
I
I = Input
O = Output
PIN CONFIGURAT ION
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
TOP VIEW
(Not to Scale)
AGND
AIN+
AIN–
CLKIN
FSI
FSEL
SF
DV
DD
FSO
DOUT CLK
REFIN
REFOUT
AV
DD
TP0
TP1
TP2
TP3
DGND
DOUT
DOE
AD776
ORDE RING GUIDE
T emperature
Range
Package
Description
Package
Option
Model
AD776AQ
–40
°
C to +85
°
C
20-Pin Cerdip
Q-20
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