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參數(shù)資料
| 型號： | AD776 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 16-Bit 100 kSPS Oversampling ADC(16位100kSPS過采樣A/D轉(zhuǎn)換器) |
| 中文描述： | 16位100 kSPS的采樣ADC的（16位100ksps的過采樣的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 10/12頁 |
| 文件大?。?/td> | 257K |
| 代理商： | AD776 |
AD776
–10–
REV. A
DIGIT AL T IMING
T he CLK IN frequency and the choice of output filter mode
(FIR or Comb) determine the output sample rate of the AD776.
With FSEL LOW, the FIR filter output is selected and the out-
put rate is equal to CLK IN divided by 128
.
When FSEL is
HIGH, the Comb filter is selected and the output sample rate is
equal to CLK IN divided by
32
.
T he input sample rate (or mod-
ulator frequency) is always the CLK IN frequency divided by 2
.
T he flexible serial data output interface of the AD776 may be
configured in one of three modes. MODE A and MODE B are
used when the FIR filter output is desired. MODE C should be
selected when output from the comb filter is used. Output data
is always transmitted as 16-bit twos complement, MSB first, se-
rial words. In all modes, the FSI pin may be asserted to reset the
serial data output and synchronize internal circuits. A
DOE
pin
is available to place the DOUT pin in a high impedance state.
Configuring the appropriate timing mode is controlled by the
FSEL and SF pins. T he truth table is shown in T able IV.
T able IV. T iming Mode T ruth T able
FSE L
SF
Output Mode
0
0
1
0
1
0
A
B
C
MODE A
T he timing diagrams for MODE A are shown in Figures 14a
and 14b. If MODE A is selected, an internal multiplexer routes
serial data from the output of the FIR filter to the DOUT pin.
T he output sample rate is a function of the clock present at the
CLK IN pin where:
Output Sample Rate
=
CLKIN
/128
A continuous serial output clock, DOUT CLK , is available with
the bit rate determined by:
DOUT CLK = CLKIN/4
.
Serial data from the DOUT pin is valid on the falling edges of
DOUT = CLK . A framing signal, FSO, occurs with a period
equal to the output sample rate (Figure 14b). T he FSO signal
is HIGH during the falling edge of DOUT CLK prior to the
beginning of a new output data word.
CLKIN
FSI
DOUT CLK
FSO
DOUT
t
IO
t
DH
t
FSOHC
t
FSOHC
t
DSU
D15
D14
D13
D1
D0
ZERO (AFTER PREVIOUS D0)
4
t
CLK
t
CLK
Figure 14a. Mode A Timing
CLKIN
DOUT CLK
FSO
DOUT
VALID FOR FIRST 16 DOUT
ZERO FOR LAST 16 DOUT
VALID
128
t
CLK
CYCLES
32 DOUT CLK CYCLES
Figure 14b. Mode A Timing
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