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參數(shù)資料
| 型號(hào)： | AD776 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 16-Bit 100 kSPS Oversampling ADC(16位100kSPS過采樣A/D轉(zhuǎn)換器) |
| 中文描述： | 16位100 kSPS的采樣ADC的（16位100ksps的過采樣的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 11/12頁 |
| 文件大?。?/td> | 257K |
| 代理商： | AD776 |
AD776
REV. A
–11–
MODE B
T he timing diagrams for MODE B are shown in Figures 15a
and 15b. If Mode B is selected, the internal multiplexer routes
serial data from the output of the FIR filter to the DOUT pin
similar to MODE A. T he output sample rate is a function of the
clock present at the CLK IN pin where:
Output Sample Rate = CLKIN/128.
A continuous serial output clock, DOUT CLK , is available with
the bit rate determined by:
DOUT CLK = CLKIN/4.
Note that serial data present at the DOUT pin is valid on the
rising edges of DOUT CLK . T he framing signal, FSO, occurs
with a period equal to the output sample rate. In MODE B, the
FSO signal goes LOW at the beginning of the output data word
and remains LOW until the entire word is transmitted.
CLKIN
FSI
DOUT CLK
FSO
DOUT
D15
D14
D13
D0
LOW FOR D15 - D0
ZERO (AFTER PREVIOUS D0)
t
DH
8
t
CLK
t
FSOSD
t
DSU
t
FSOHD
t
CLK
D1
Figure 15a. Mode B Timing
DOUT CLK
FSO
DOUT
32 DOUT CLK CYCLES
VALID FOR FIRST 16 DOUT CLK CYCLES
ZERO FOR LAST 16 DOUT CLK CYCLES
VALID
LOW (ASSERTED) FOR FIRST
16 DOUT CLK CYCLES
HIGH (DEASSERTED) FOR LAST
16 DOUT CLK CYCLES
Figure 15b. Mode B Timing
MODE C
T he timing diagrams for MODE C are shown in Figure 16. If
Mode C is selected, the internal multiplexer routes serial data
from the output of the COMB filter to the DOUT pin, bypass-
ing the FIR filter. T he output sample rate is a function of the
clock present at the CLK IN pin where:
Output Sample Rate = CLKIN/32.
A continuous serial output clock, DOUT CLK , is available
with the bit rate determined by:
DOUT CLK = CLKIN/2
.
Serial output data is valid on the falling edges of DOUT CLK .
T he framing signal, FSO, occurs with a period equal to the out-
put sample rate. T he FSO signal is HIGH during the falling
edge of DOUT CLK prior to transmission of the next output
data word. Note that in MODE C, this is also when the LSB,
(D0), of the previous data word is valid.
CLKIN
FSI
DOUT CLK
FSO
DOUT
t
DH
t
DSU
D15
D14
D13
D1
D0
t
FSIL
t
IO
D15
D1
D0
32 DOUT CLK CYCLES
Figure 16. Mode C Timing
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