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參數(shù)資料
| 型號(hào)： | AD776 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 16-Bit 100 kSPS Oversampling ADC(16位100kSPS過(guò)采樣A/D轉(zhuǎn)換器) |
| 中文描述： | 16位100 kSPS的采樣ADC的（16位100ksps的過(guò)采樣的A / D轉(zhuǎn)換器） |
| 文件頁(yè)數(shù)： | 12/12頁(yè) |
| 文件大小： | 257K |
| 代理商： | AD776 |
AD776
–12–
REV. A
C
P
FSI Operation
A frame sync input is available to the user on the FSI pin to
reset the serial data output and synchronize internal circuits.
Referring to Figure 17, the FSI pin is sampled on the falling
edge of CLK IN. T he FSI pin must adhere to several conditions
depending on which mode is being used as follows:
FSI in MODE A, MODE B
1. FSI should be a periodic signal occurring every 32 DOUT
CLK periods.
2. FSI must be deasserted for at least 2 CLK IN periods prior
to being asserted.
3. FSI must be synchronized to CLK IN to meet the timing re-
quirements outlined in Figure 17.
FSI in MODE C
1. FSI should be a periodic signal occurring every 16 DOUT
CLK periods.
2. FSI must be deasserted for at least 2 CLK IN periods prior
to being asserted.
3. FSI must be synchronized to CLK IN to meet the timing re-
quirements outlined in Figure 17.
CLKIN
FSI
DOUT CLK
t
FSS
t
D
t
CL
t
CH
t
CLK
t
CKOUT
t
DOD
t
DOD
t
FSH
t
R
, t
F
Figure 17. Frame Sync Input (FSI) Timing (FIR Filter Out-
put Mode)
Synchronizing T wo Channels
T he FSI pin is useful when multiple AD776s are used together
and must be synchronized. In such a case, a single pulse may be
applied to FSI inputs of the converters. T his causes the internal
“state-machine” of the AD776 to be reset. T hus, the internal
clocking for both the analog and digital circuitry of each individual
converter is synchronized and inphase. In the case of a single FSI
pulse, it must still adhere to the timing outlined in Figure 17.
T hree-Stating the DOUT Pin (
DOE
)
In all modes DOUT may be three-stated using the
DOE
pin.
Operation of the
DOE
input is shown in Figure 18. When the
DOE
input is HIGH, serial data will be present and active at the
DOUT pin. When
DOE
is brought LOW, the DOUT pin is
placed in a high-impedance state.
DOE
is completely asynchro-
nous and independent of input and output clocks. DOUT load-
ing will affect actual performance.
t
DD
t
DF
DOE
DATA OUT
Figure 18. Data Output Timing
INT E RFACING T HE AD776
T he AD776 is designed for ease of interface with a variety of
popular processors. T he following diagrams illustrate typical
configurations:
FSO
DOUT
DOUT CLK
DOE
SF
AD776
RFS0
DR0
SCLK0
ADSP-21xx
LOGIC 0
PC5/FSR
PC7/SRD
PC6/SCK
DSP56001
FSR
DR
CLKR
TMS320C25
FSO
DOUT
DOUT CLK
DOE
SF
AD776
LOGIC 0
FSO
DOUT
DOUT CLK
DOE
SF
AD776
LOGIC 0
Figure 19.
OUT LINE DIME NSIONS
Dimensions shown in inches and (mm).
20-Pin Cerdip (Q-20)
0.320 (8.13)
0.290 (7.37)
0.015 (0.38)
0.008 (0.20)
15
°
0
°
PIN 1
0.310 (7.87)
0.220 (5.59)
10
11
1
20
1.060 (26.92) MAX
0.200
(5.08)
MAX
0.023 (0.58)
0.014 (0.36)
0.200 (5.08)
0.125 (3.18)
0.070 (1.78)
0.030 (0.76)
0.060 (1.52)
0.015 (0.38)
SEATING
PLANE
0.100 (2.54)
BSC
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