參數(shù)資料
型號: AD7765BRUZ
廠商: Analog Devices Inc
文件頁數(shù): 24/33頁
文件大?。?/td> 0K
描述: IC ADC 24BIT S/D 156KSPS 28TSSOP
標準包裝: 50
位數(shù): 24
采樣率(每秒): 156k
數(shù)據(jù)接口: 串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 371mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-TSSOP(0.173",4.40mm 寬)
供應商設備封裝: 28-TSSOP
包裝: 管件
輸入數(shù)目和類型: 1 個差分,單極;1 個差分,雙極
產(chǎn)品目錄頁面: 779 (CN2011-ZH PDF)
AD7765
Rev. A | Page 29 of 32
GAIN REGISTER—ADDRESS 0x0004
Non-Bit-Mapped, Default Value 0xA000
The gain register is scaled such that 0x8000 corresponds to a
gain of 1.0. The default value of this register is 1.25 (0xA000).
This results in a full-scale digital output when the input is at
80% of VREF+, tying in with the maximum analog input range
of ±80% of VREF+ p-p.
OVERRANGE REGISTER—ADDRESS 0x0005
Non-Bit-Mapped, Default Value 0xCCCC
The overrange register value is compared with the output of the
first decimation filter to obtain an overload indication with
minimum propagation delay. This is prior to any gain scaling or
offset adjustment. The default value is 0xCCCC, which corre-
sponds to 80% of VREF+ (the maximum permitted analog input
voltage). Assuming VREF+ = 4.096 V, the bit is then set when the
input voltage exceeds approximately 6.55 V p-p differential. The
overrange bit is set immediately if the analog input voltage
exceeds 100% of VREF+ for more than four consecutive samples
at the modulator rate.
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