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參數(shù)資料
| 型號： | AD7765BRUZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/33頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 24BIT S/D 156KSPS 28TSSOP |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 156k |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 371mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-TSSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個差分，單極；1 個差分，雙極 |
| 產(chǎn)品目錄頁面： | 779 (CN2011-ZH PDF) |
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AD7765
Rev. A | Page 20 of 32
AD7765 INTERFACE
READING DATA
The AD7765 uses an SPI-compatible serial interface. The
timing diagram in Figure 2 shows how the AD7765 transmits
its conversion results.
The data read from the AD7765 is clocked out using the serial
clock output (SCO). The SCO frequency is half that of the
MCLK input to the AD7765.
The conversion result output on the serial data output (SDO)
line is framed by the frame synchronization output, FSO
Table 9. Status Bits During Data Read
, which
is sent logic low for 32 SCO cycles. Each bit of the new
conversion result is clocked onto the SDO line on the rising
SCO edge and is valid on the falling SCO edge. The 32-bit result
consists of the 24 data bits followed by five status bits followed
further by three zeros. The five status bits are listed in Table 9
and described below the table.
D7
D6
D5
D4
D3
FILTER-SETTLE
OVR
LPWR
DEC_RATE 1
Don’t care
The FILTER-SETTLE bit indicates whether the data output
from the AD7765 is valid. After resetting the device (using
the RESET pin) or clearing the digital filter (using the
The OVR (overrange) bit is described in the
SYNC pin), the FILTER-SETTLE bit goes logic low to
indicate that the full settling time of the filter has not yet
passed and that the data is not yet valid. The FILTER-
SETTLE bit also goes to zero when the input to the part
has asserted the overrange alerts.
Alerts section.
The LPWR bit is set to logic high when the AD7765 is
operating in low power mode. See the Power Modes
section for further details.
The DEC_RATE 1 and DEC_RATE 0 bits indicate the
decimation ratio used. Table 10 is a truth table for the
decimation rate bits.
Table 10. Truth Table
Decimate
DEC_RATE 1
128×
1
256×
0
READING STATUS AND OTHER REGISTERS
The AD7765 features a gain correction register, an overrange
register, and a read-only status register. To read back the
contents of these registers, the user must first write to the
control register of the device and set the bit that corresponds
to the register to be read. The next read operation outputs the
contents of the selected register (on the SDO pin) instead of a
conversion result.
To ensure that the next read cycle contains the contents of the
register written to, the write operation to that register must be
completed a minimum of 8 × tSCO before the falling edge of FSO
The
,
which indicates the start of the next read cycle. See Figure 4 for
further details.
AD7765 Registers section provides more information on
the relevant bits in the control register.
WRITING TO THE AD7765
A write operation to the AD7765 is shown in Figure 3. The
serial writing operation is synchronous to the SCO signal. The
status of the frame synchronization input, FSI, is checked on the
falling edge of the SCO signal. If the FSI line is low, then the
first data bit on the serial data in (SDI) line is latched in on the
next SCO falling edge.
Set the active edge of the FSI signal to occur at a position when
the SCO signal is high or low to allow setup and hold times
from the SCO falling edge to be met. The width of the
FSI
signal can be set to between 1 and 32 SCO periods wide. A
second, or subsequent, falling edge that occurs before
32 SCO periods have elapsed is ignored.
details the format for the serial data being written to
the AD7765 through the SDI pin. Thirty-two bits are required
for a write operation. The first 16 bits are used to select the
register address for which the data being read is intended. The
second 16 bits contain the data for the selected register.
Writing to the AD7765 is allowed at any time, even while
reading a conversion result. Note that, after writing to the
devices, valid data is not output until after the settling time for
the filter has elapsed. The FILTER-SETTLE status bit is asserted
at this point to indicate that the filter has settled and that valid
data is available at the output.
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| AD7765BRUZ-REEL7 | 功能描述:IC ADC 24BIT S/D 156KSPS 28TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個單端，單極；1 個單端，雙極 |
| AD7766 | 制造商:AD 制造商全稱:Analog Devices 功能描述:24-Bit, 8.5 mW, 109 dB, 128/64/32 kSPS ADCs |
| AD7766-1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:24-Bit, 8.5 mW, 109 dB, 128/64/32 kSPS ADCs |
| AD7766-2 | 制造商:AD 制造商全稱:Analog Devices 功能描述:24-Bit, 8.5 mW, 109 dB, 128/64/32 kSPS ADCs |
| AD7766BRUZ | 功能描述:IC ADC 24BIT 128KSPS SAR 16TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個單端，單極；2 個差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
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