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參數(shù)資料
| 型號： | AD7265 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Differential Input, Dual 1 MSPS, 12-Bit, 3-Channel SAR ADC |
| 中文描述： | 差分輸入，雙1 MSPS的12位，3通道SAR型ADC |
| 文件頁數(shù)： | 8/16頁 |
| 文件大?。?/td> | 706K |
| 代理商： | AD7265 |
AD7265
Preliminary Technical Data
TERMINOLOGY
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Track-and-Hold Acquisition Time
The track-and-hold amplifier returns into track mode after the
end of conversion. Track-and-hold acquisition time is the time
required for the output of the track-and-hold amplifier to reach
its final value, within ±1/2 LSB, after the end of conversion.
Integral Nonlinearity
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The
endpoints of the transfer function are zero scale, a point 1 LSB
below the first code transition, and full scale, a point 1 LSB
above the last code transition.
Signal to (Noise + Distortion) Ratio
This is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the sum of all non-fundamental
signals up to half the sampling frequency (f
S
/2), excluding dc.
The ratio is dependent on the number of quantization levels in
the digitization process; the more levels, the smaller the
quantization noise. The theoretical signal to (noise + distortion)
ratio for an ideal N-bit converter with a sine wave input is given
by:
Offset Error
This applies to Straight Binary output coding. It is the deviation
of the first code transition (00 . . . 000) to (00 . . . 001) from the
ideal, i.e., AGND + 1 LSB.
Offset Error Match
This is the worst case difference in Offset Error between any of
the twelve channels.
Signal to (Noise + Distortion) = (6.02N + 1.76) dB
Thus for a 12-bit converter, this is 74 dB.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7265 it is defined as:
Gain Error
This applies to Straight Binary output coding. It is the deviation
of the last code transition (111 . . . 110) to (111 . . . 111) from the
ideal (i.e., VREF – 1 LSB) after the offset error has been adjusted
out.
1
2
6
2
5
2
4
2
3
2
2
log
20
)
(
V
V
V
V
V
V
dB
THD
+
+
+
+
=
Gain Error Match
This is the difference in Gain Error between the two channels.
where V
1
is the rms amplitude of the fundamental and V
2
, V
3
,
V
4
, V
5
and V
6
are the rms amplitudes of the second through the
sixth harmonics.
Zero Code Error
This applies when using twos complement output coding in
particular with the 2 x V
REF
input range as –V
REF
to +V
REF
biased
about the V
REF
point. It is the deviation of the midscale
transition (all 1s to all 0s) from the ideal V
IN
voltage, i.e., V
REF
- 1
LSB.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but for
ADCs where the harmonics are buried in the noise floor, it will
be a noise peak.
Zero Code Error Match
This refers to the difference in Zero Code Error between the
two channels.
Channel-to-Channel Isolation
Channel-to-channel isolation is a measure of the level of
crosstalk between channels. It is measured by applying a full-
scale (2 x V
REF
), 455kHz sine wave signal to all unselected input
channels and determining how much that signal is attenuated in
the selected channel with a 10 kHz signal (0 V to V
REF
). The
figure given is the worst-case across all twelve channels for the
AD7265.
Positive Gain Error
This applies when using twos complement output coding in
particular with the 2 x V
REF
input range as –V
REF
to +V
REF
biased
about the V
REF
point. It is the deviation of the last code
transition (011…110) to (011…111) from the ideal (i.e., + V
REF
-
1 LSB) after the Zero Code Error has been adjusted out.
Rev. PrA | Page 8 of 16
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|---|---|
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