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參數(shù)資料
| 型號(hào)： | AD7265 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Differential Input, Dual 1 MSPS, 12-Bit, 3-Channel SAR ADC |
| 中文描述： | 差分輸入，雙1 MSPS的12位，3通道SAR型ADC |
| 文件頁數(shù)： | 14/16頁 |
| 文件大?。?/td> | 706K |
| 代理商： | AD7265 |
AD7265
Preliminary Technical Data
To exit this mode of operation and power up the AD7265 again,
a dummy conversion is performed. On the falling edge of CS,
the device begins to power up, and continues to power up as
long as CS is held low until after the falling edge of the 10
th
SCLK. The device is fully powered up after approximately 1 μs
has elapsed, and valid data results from the next conversion, as
shown in Figure 10. If CS is brought high before the second
falling edge of SCLK, the AD7265 again goes into partial power-
down. This avoids accidental power-up due to glitches on the
CS line. Although the device may begin to power up on the
falling edge of CS, it powers down again on the rising edge of
CS. If the AD7265 is already in partial power-down mode and
CS is brought high between the second and 10
th
falling edges of
SCLK, the device enters full power-down mode.
FULL POWER-DOWN MODE
This mode is intended for use in applications where throughput
rates slower than those in the partial power-down mode are
required, as power-up from a full power-down takes substan-
tially longer than that from partial power-down. This mode is
more suited to applications where a series of conversions
performed at a relatively high throughput rate are followed by a
long period of inactivity and thus power-down. When the
AD7265 is in full power-down, all analog circuitry is powered
down. Full power-down is entered in a similar way as partial
power-down, except the timing sequence shown in Figure 9
must be executed twice. The conversion process must be
interrupted in a similar fashion by bringing CS high anywhere
after the second falling edge of SCLK and before the 10
th
falling
edge of SCLK. The device enters partial power-down at this
point. To reach full power-down, the next conversion cycle must
be interrupted in the same way, as shown in Figure TBD. Once
CS has been brought high in this window of SCLKs, the part
powers down completely.
Note that it is not necessary to complete the 14 SCLKs once CS
has been brought high to enter a power-down mode.
To exit full power-down and power the AD7265 up again, a
dummy conversion is performed, as when powering up from
partial power-down. On the falling edge of CS, the device
begins to power up and continues to power up as long as CS is
held low until after the falling edge of the 10
th
SCLK. The
power-up time required must elapse before a conversion can be
initiated, as shown in Figure TBD. See the Power-Up Times
section for the power-up times associated with the AD7265.
0
1
A
10
14
1
14
SCLK
INVALID DATA
VALID DATA
D
OUT
A
D
OUT
B
CS
T
POWER-UP
THE PART BEGINS
TO POWER-UP
THE PART IS FULLY POWERED UP,
SEE POWER-UP TIMES SECTION
Figure 10. Exiting Partial Power-Down Mode
Rev. PrA | Page 14 of 16
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7265ACP | 制造商:Analog Devices 功能描述: |
| AD7265ASU | 制造商:Analog Devices 功能描述: |
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| AD7265BCPZ | 功能描述:IC ADC 12BIT SRL 1MSPS 32LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個(gè)單端，單極；2 個(gè)差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| AD7265BCPZ-REEL | 功能描述:IC ADC 12BIT 3CHAN 1MSPS 32LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):16 采樣率（每秒）:15 數(shù)據(jù)接口:MICROWIRE?，串行，SPI? 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:480µW 電壓電源:單電源 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:38-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:38-QFN（5x7） 包裝:帶卷 (TR) 輸入數(shù)目和類型:16 個(gè)單端，雙極；8 個(gè)差分，雙極 配用:DC1011A-C-ND - BOARD DELTA SIGMA ADC LTC2494 |
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