參數(shù)資料
型號(hào)： AD7265
廠商： Analog Devices, Inc.
英文描述： Differential Input, Dual 1 MSPS, 12-Bit, 3-Channel SAR ADC
中文描述： 差分輸入，雙1 MSPS的12位，3通道SAR型ADC
文件頁(yè)數(shù)： 11/16頁(yè)
文件大?。?/td> 706K
代理商： AD7265
Preliminary Technical Data
AD7265
ANALOG INPUT
The analog inputs of the AD7265 may be configured as single
ended or true differential via the SGL/DIFF logic pin, as shown
in Figure 5. On the falling edge of CS, point A, the logic level of
the SGL/DIFF pin is checked to determine the configuration of
the analog input channels for the
next
conversion. If this pin is
tied to a logic low, the analog input channels to each on-chip
ADC are set up as three true differential pairs. If this pin is at a
logic high when CS goes low, the analog input channels to each
on-chip ADC are set up as six single-ended analog inputs. In
Figure 5 at point A, the SGL/DIFF pin is at a logic high so the
analog inputs are configured as single-ended for the next
conversion, i.e. sampling point B. At point B, the logic level of
the SGL/DIFF pin has changed to low; there fore, the analog
inputs are configured as differential for the next conversion
after this one, even though this current conversion is on single
ended configured inputs.
The channels to be converted on simultaneously are selected via
the multiplexer address inputs A0 to A2. The logic states of
these pins are also checked upon the falling edge of CS and the
channels are chosen for the
next
conversion. The selected input
channels are decoded as shown in Table 6.
The analog input range of the AD7265 can be selected as 0 V to
V
REF
or 0 V to 2 × V
REF
via the RANGE pin. This selection is
made in a similar fashion to that of the SGL/DIFF pin by
checking the logic state of the RANGE pin upon the falling edge
of CS. The analog input range is set up for the
next
conversion.
If this pin is tied to a logic low upon the falling edge of CS, the
analog input range for the next conversion is 0 V to V
REF
. If this
pin is tied to a logic high upon the falling edge of CS, the analog
input range for the next conversion is 0 V to 2 × V
REF
.
OUTPUT CODING
The AD7265 output coding is set to either twos complement or
straight binary depending on which analog input configuration
is selected for a conversion. Table 5 shows which output coding
scheme is used for each possible analog input configuration.
Table 5 AD7265 Output Coding
SGL/DIFF
Range
DIFF
0 V to V
REF
DIFF
0 V to 2 × V
REF
SGL
0 V to V
REF
SGL
0 V to 2 × V
REF
PSUEDO DIFF
0 V to V
REF
PSUEDO DIFF
0 V to 2 × V
REF
0
A
CS
SCLK
SGL/DIFF
1
14
1
14
B
Output Coding
Twos Complement
Twos Complement
Straight Binary
Twos Complement
Straight Binary
Straight Binary
Figure 5. Selecting Differential or Single Ended Configuration
Table 6. Analog Input Type and Channel Selection
SGL/DIFF
A2
1
0
1
0
1
0
1
0
1
1
1
1
0
0
0
0
0
0
0
0
0
1
0
1
A1
0
0
1
1
0
0
0
0
1
1
0
0
A0
0
1
0
1
0
1
0
1
0
1
0
1
ADC A
V
IN–
AGND
AGND
AGND
AGND
AGND
AGND
V
A2
V
A2
V
A4
V
A4
V
A6
V
A6
ADC B
V
IN–
AGND
AGND
AGND
AGND
AGND
AGND
V
B2
V
B2
V
B4
V
B4
V
B6
V
B6
Comment
Single Ended
Single Ended
Single Ended
Single Ended
Single Ended
Single Ended
Fully Differential
Pseudodifferential
Fully Differential
Pseudodifferential
Fully Differential
Pseudodifferential
V
IN+
V
A1
V
A2
V
A3
V
A4
V
A5
V
A6
V
A1
V
A1
V
A3
V
A3
V
A5
V
A5
V
IN+
V
B1
V
B2
V
B3
V
B4
V
B5
V
B6
V
B1
V
B1
V
B3
V
B3
V
B5
V
B5
Rev. PrA | Page 11 of 16
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