參數(shù)資料
型號(hào)： AD7265
廠商： Analog Devices, Inc.
英文描述： Differential Input, Dual 1 MSPS, 12-Bit, 3-Channel SAR ADC
中文描述： 差分輸入，雙1 MSPS的12位，3通道SAR型ADC
文件頁(yè)數(shù)： 4/16頁(yè)
文件大小： 706K
代理商： AD7265
AD7265
Preliminary Technical Data
Parameter
LOGIC OUTPUTS
Output High Voltage, V
OH
Output Low Voltage, V
OL
Floating State Leakage Current
Floating State Output Capacitance
3
Output Coding
CONVERSION RATE
Conversion Time
Track/Hold Acquisition Time
3
Throughput Rate
POWER REQUIREMENTS
V
DD
V
DRIVE
I
DD6
Normal Mode (Static)
Operational, f
s
= 1 MSPS
Partial Power-Down Mode
Partial Power-Down Mode
Full Power-Down Mode
Power Dissipation
6
Normal Mode (Operational)
Partial Power-Down (Static)
Full Power-Down (Static)
NOTES
1
Temperature ranges as follows: -40°C to +125°C
2
See
section.
Terminology
3
Sample tested during initial release to ensure compliance.
4
Relates to Pins D
CAP
A or D
CAP
B.
5
See Reference section for D
CAP
A, D
CAP
B output impedances.
6
See Power Versus Throughput Rate section.
TIMING SPECIFICATIONS
Table 2. AV
DD
= DV
DD
= 2.7 V to 5.25 V, V
DRIVE
= 2.7 V to 5.25 V, T
A
= T
MAX
to T
MIN
, unless otherwise noted
Parameter
Limit at T
MIN
, T
MAX
Unit
f
SCLK
10
kHz min
20
MHz max
t
CONVERT
14 × t
SCLK
ns max
700
ns max
t
QUIET
35
ns max
t
2
10
ns min
t
3
TBD
ns max
t
4
TBD
ns max
t
5
0.4t
SCLK
ns min
t
6
0.4t
SCLK
ns min
t
7
TBD
ns min
t
8
25
ns max
t
9
TBD
ns min
TBD
ns max
Specification
V
DRIVE
– 0.2
0.4
±1
10
Straight (Natural) Binary
Twos Complement
14
100
TBD
2.7/5.25
2.7/5.25
TBD
3.3
2.3
TBD
TBD
TBD
16.5
TBD
TBD
Unit
V min
V max
μA max
pF max
Test Conditions/Comments
SGL/DIFF = 1 with 0 V to V
REF
range selected
SGL/DIFF = 0; SGL/DIFF = 1 with 0 V to 2 × V
REF
range
TBD ns with SCLK = 16 MHz
Digital I/Ps = 0 V or V
DRIVE
V
DD
= 5 V
V
DD
= 3 V
f
s
= 200 kSPS
Static
V
DD
= 5 V
SCLK Cycles
ns max
MSPS max
V min/V max
V min/V max
mA max
mA max
mA max
mA max
μA max
μA max
mW max
mW max
mW max
Description
t
SCLK
= 1/f
SCLK
f
SCLK
= 20 MHz,
Minimum time between end of serial read and next falling edge of CS
CS to SCLK setup time
Delay from CS until D
OUT
A and D
OUT
B are three-state disabled
Data access time after SCLK falling edge.
SCLK low pulse width
SCLK high pulse width
SCLK to data valid hold time
CS rising edge to D
OUT
A, D
OUT
B, high impedance
SCLK falling edge to D
OUT
A, D
OUT
B, high impedance
SCLK falling edge to D
OUT
A, D
OUT
B, high impedance
Rev. PrA | Page 4 of 16
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