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參數(shù)資料
| 型號： | AD5233BRUZ50-R7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DGTL POT QUAD 64POS 24-TSSOP |
| 標準包裝： | 1,000 |
| 接片： | 64 |
| 電阻（歐姆）： | 50k |
| 電路數(shù)： | 4 |
| 溫度系數(shù)： | 標準值 600 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | 4 線 SPI（芯片選擇） |
| 電源電壓： | 2.7 V ~ 5.5 V，±2.25 V ~ 2.75 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-TSSOP |
| 包裝： | 帶卷 (TR) |
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AD5233
Rev. B | Page 17 of 32
DAISY-CHAIN OPERATION
The ground pin of the AD5233 device is used primarily as a
digital ground reference, which needs to be tied to the PCB’s
common ground. The digital input control signals to the
AD5233 must be referenced to the device ground pin (GND)
and satisfy the logic level defined in the Specifications section.
An internal level-shift circuit ensures that the common-mode
voltage range of the three terminals extends from VSS to VDD,
regardless of the digital input level.
The serial data output (SDO) pin serves two purposes. It can
be used to read the contents of the wiper setting and EEMEM
values using Instruction 10 and Instruction 9, respectively.
The remaining instructions (0 to 8, 11 to 15) are valid for
daisy-chaining multiple devices in simultaneous operations.
Daisy-chaining minimizes the number of port pins required
from the controlling IC (Figure 39). The SDO pin contains an
open-drain N-channel FET that requires a pull-up resistor, if
this function is used. As shown in Figure 39, users need to tie
the SDO pin of one package to the SDI pin of the next package.
POWER-UP SEQUENCE
Because there are diodes to limit the voltage compliance at
Terminal A, Terminal B, and Terminal W (see Figure 40), it is
important to power on VDD/VSS first before applying any voltage
to Terminal A, Terminal B, and Terminal W. Otherwise, the
diode is forward-biased such that VDD/VSS are powered unin-
tentionally. For example, applying 5 V across the A and B
terminals prior to VDD causes the VDD terminal to exhibit 4.3 V.
It is not destructive to the device, but it might affect the rest of
the system. The ideal power-up sequence is GND, VDD, VSS,
digital inputs, and VA/VB/VW. The order of powering VA, VB,
VW, and digital inputs is not important as long as they are
powered after VDD/VSS.
Users might need to increase the clock period, because the
pull-up resistor and the capacitive loading at the SDO to SDI
interface might require an additional time delay between
subsequent packages. When two AD5233s are daisy-chained,
32 bits of data is required. The first 16 bits go to U2 and the
second 16 bits go to U1. CS should be kept low until all 32 bits
are clocked into their respective serial registers. CS is then
pulled high to complete the operation.
SDI
SDO
CLK
RP
2k
SDI
SDO
CLK
U1
U2
AD5233
CS
+V
0
279
4-
0
40
MICRO-
CONTROLLER
Regardless of the power-up sequence and the ramp rates of the
power supplies, once VDD/VSS are powered, the power-on preset
remains effective, which restores the EEMEM values to the
RDAC registers.
LATCHED DIGITAL OUTPUTS
A pair of digital outputs, O1 and O2, is available on the AD5233.
These outputs provide a nonvolatile Logic 0 or Logic 1 setting.
O1 and O2 are standard CMOS logic outputs, shown in Figure 41.
These outputs are ideal to replace the functions often provided
by DIP switches. In addition, they can be used to drive other
standard CMOS logic-controlled parts that need an occasional
setting change. Pin O1 and Pin O2 default to Logic 1, and they
can drive up to 50 mA of load at 5 V/25°C.
Figure 39. Daisy-Chain Configuration Using SDO
TERMINAL VOLTAGE OPERATION RANGE
The AD5233’s positive VDD and negative VSS power supplies
define the boundary conditions for proper 3-terminal digital
potentiometer operation. Supply signals present on Terminal A,
Terminal B, and Terminal W that exceed VDD or VSS are clamped
by the internal forward-biased diodes (see Figure 40).
VDD
GND
OUTPUTS
O1 AND O2
PINS
02
79
4
-04
2
VSS
VDD
A
W
B
02
79
4-
04
1
Figure 41. Logic Output O1 and Logic Output O2
Figure 40. Maximum Terminal Voltages Set by VDD and VSS
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