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參數(shù)資料
型號(hào): AD5233BRUZ50-R7
廠商: Analog Devices Inc
文件頁(yè)數(shù): 5/32頁(yè)
文件大?。?/td> 0K
描述: IC DGTL POT QUAD 64POS 24-TSSOP
標(biāo)準(zhǔn)包裝: 1,000
接片: 64
電阻(歐姆): 50k
電路數(shù): 4
溫度系數(shù): 標(biāo)準(zhǔn)值 600 ppm/°C
存儲(chǔ)器類型: 非易失
接口: 4 線 SPI(芯片選擇)
電源電壓: 2.7 V ~ 5.5 V,±2.25 V ~ 2.75 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 24-TSSOP
包裝: 帶卷 (TR)
AD5233
Rev. B | Page 13 of 32
TEST CIRCUITS
Figure 25 to Figure 35 define the test conditions used in the specifications.
A
W
B
NC
IW
DUT
VMS
NC = NO CONNECT
02
79
4-
02
6
Figure 25. Resistor Position Nonlinearity Error
(Rheostat Operation; R-INL, R-DNL)
A
W
B
DUT
VMS
V+
V+ = VDD
1LSB = V+/2N
0
279
4-
0
27
Figure 26. Potentiometer Divider Nonlinearity Error (INL, DNL)
A
W
B
DUT
IW
VMS1
VMS2
VW
RW = [VMS1 – VMS2]/IW
0
27
94
-028
Figure 27. Wiper Resistance
A
W
B
VMS
V+ = VDD ±10%
PSRR (dB) = 20 log
VA
VDD
PSS (%/%) =
ΔVMS%
ΔVDD%
ΔVMS
ΔVDD
()
V+
02
79
4-
02
9
Figure 28. Power Supply Sensitivity (PSS, PSRR)
OFFSET BIAS
OFFSET
GND
A DUT B
W
5V
VIN
VOUT
OP279
02
79
4-
03
0
Figure 29. Inverting Gain
OFFSET BIAS
OFFSET
GND
AB
DUT
W
5V
VIN
VOUT
OP279
0
27
94
-03
1
Figure 30. Noninverting Gain
OFFSET
GND
A
B
DUT
W
+15V
VIN
VOUT
OP42
–15V
2.5V
02
79
4-
03
2
Figure 31. Gain vs. Frequency
+
DUT
CODE = 0x00
0.1V
VBIAS
RSW =
0.1V
ISW
W
B
A = NC
0
2
79
4-
0
33
Figure 32. Incremental On Resistance
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