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參數(shù)資料
| 型號： | AD5233BRUZ50-R7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 21/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DGTL POT QUAD 64POS 24-TSSOP |
| 標準包裝： | 1,000 |
| 接片： | 64 |
| 電阻（歐姆）： | 50k |
| 電路數(shù)： | 4 |
| 溫度系數(shù)： | 標準值 600 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | 4 線 SPI（芯片選擇） |
| 電源電壓： | 2.7 V ~ 5.5 V，±2.25 V ~ 2.75 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-TSSOP |
| 包裝： | 帶卷 (TR) |
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AD5233
Rev. B | Page 28 of 32
In voltage divider mode, by paralleling a discrete resistor as
shown in Figure 61, a proportionately lower voltage appears at
Terminal A to Terminal B. This translates into a finer degree of
precision because the step size at Terminal W is smaller.
RESISTANCE TOLERANCE, DRIFT, AND
TEMPERATURE MISMATCH CONSIDERATIONS
R2
R3
VDD
R1
B
W
0
A
02
79
4-
06
2
Figure 61. Lowering the Nominal Resistance
The voltage can be found as follows:
DD
AB
W
V
D
R
D
V
×
+
=
64
||
)
||
(
)
(
2
3
2
(19)
In a rheostat mode operation such as gain control (see Figure 64),
the tolerance mismatch between the digital potentiometer and
the discrete resistor can cause repeatability issues among various
systems. Because of the inherent matching of the silicon process,
it is practical to apply the dual- or multiple-channel device in
this type of application. As such, R1 can be replaced by one of
the channels of the digital potentiometer and programmed to a
specific value. R2 can be used for the adjustable gain. Although
it adds cost, this approach minimizes the tolerance and
temperature coefficient mismatch between R1 and R2. This
approach also tracks the resistance drift over time. As a result,
all nonideal parameters become less sensitive to the system
variations.
AD8601
+
–
Vi
U1
VO
C1
A
B
W
R2
R1*
*REPLACED WITH ANOTHER
CHANNEL OF RDAC
0
27
94
-0
65
steps change linearly. On the other hand, log taper adjustment
is usually preferred in applications such as audio control.
Figure 62 shows another type of resistance scaling. In this
configuration, the smaller the R2 with respect to R1, the
more the pseudo log taper characteristic of the circuit behaves.
R1
R2
VO
Vi
A
B
W
0
27
94
-06
3
Figure 64. Linear Gain Control with Tracking Resistance Tolerance
and Temperature Coefficient
RDAC CIRCUIT SIMULATION MODEL
The internal parasitic capacitances and the external load
dominate the ac characteristics of the RDACs. Configured as
a potentiometer divider, the 3 dB bandwidth of the AD5233
(10 kΩ resistor) measures 370 kHz at half scale. Figure 14
provides the large signal bode plot characteristics. A parasitic
simulation model is shown in Figure 65.
Figure 62. Resistor Scaling with Pseudo Log Adjustment Characteristics
DOUBLING THE RESOLUTION
Borrowing from Analog Devices’ patented RDAC segmentation
technique, the user can configure three channels of AD5233, as
RP =
RAB/64), with RDAC3, the user can double the resolution of
AD5233 from 6 bits to 12 bits. One might think that moving
RDAC1 and RDAC2 together would form the coarse 6-bit
resolution, and then moving RDAC3 would form the finer
6-bit resolution. As a result, the effective resolution would
become 12 bits. However, the precision of this circuit remains
only 6-bit accurate and the programming can be complicated.
A
RDAC
10k
W
CB
35pF
CA
35pF
CW
35pF
B
02
79
4-
06
6
RDAC1
A1
B1
VA
W3
RDAC3
A3
B3
RDAC2
A2
B2
RP
02
79
4-
0
64
Figure 65. RDAC Circuit Simulation Model for RDAC = 10 kΩ
The following code provides a macromodel net list for the
10 kΩ RDAC:
Listing I. spice model net list
.PARAM D = 64, RDAC = 10E3
*
.SUBCKT DPOT (A, W, B)
*
CA
A
0
35E-12
RWA
A
W
{(1-D/64)* RDAC + 15}
CW
W
0
35-12
RWB
W
B
{D/64 * RDAC + 15}
CB
B
0
35E-12
*
.ENDS DPOT
Figure 63. Doubling AD5233 from 6 Bits to 12 Bits
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