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| 型號： | AD5233BRUZ50-R7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 28/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DGTL POT QUAD 64POS 24-TSSOP |
| 標準包裝： | 1,000 |
| 接片： | 64 |
| 電阻（歐姆）： | 50k |
| 電路數(shù)： | 4 |
| 溫度系數(shù)： | 標準值 600 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | 4 線 SPI（芯片選擇） |
| 電源電壓： | 2.7 V ~ 5.5 V，±2.25 V ~ 2.75 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-TSSOP |
| 包裝： | 帶卷 (TR) |
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AD5233
Rev. B | Page 5 of 32
TIMING CHARACTERISTICS
VDD = 3 V to 5.5 V, VSS = 0 V, and 40°C < TA < +85°C, unless otherwise noted.
Table 2.
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
INTERFACE TIMING CHARACTERISTICS2, 3
Clock Cycle Time (tCYC)
t1
20
ns
CS Setup Time
t2
10
ns
CLK Shutdown Time to CS Rise
t3
1
tCYC
Input Clock Pulse Width
t4, t5
Clock level high or low
10
ns
Data Setup Time
t6
From positive CLK transition
5
ns
Data Hold Time
t7
From positive CLK transition
5
ns
CS to SDO-SPI Line Acquire
t8
40
ns
CS to SDO-SPI Line Release
t9
50
ns
CLK to SDO Propagation Delay4
t10
RPULL-UP = 2.2 kΩ, CL < 20 pF
50
ns
CLK to SDO Data Hold Time
t11
RP = 2.2 kΩ, CL < 20 pF
0
ns
CS High Pulse Width5
t12
10
ns
CS High to CS High5
t13
4
tCYC
RDY Rise to CS Fall
t14
0
ns
CS Rise to RDY Fall Time
t15
0.1
0.15
ms
Read/Store to Nonvolatile EEMEM6
t16
Applies to Instruction 0x2, Instruction 0x3,
and Instruction 0x9
25
ms
CS Rise to Clock Rise/Fall Setup
t17
10
ns
Preset Pulse Width (Asynchronous)
tPRW
Not shown in timing diagram
50
ns
Preset Response Time to Wiper Setting
tPRESP
PR pulsed low to refresh wiper positions
70
μs
Power-On EEMEM Restore Time
tEEMEM1
RAB = 10 kΩ
140
μs
FLASH/EE MEMORY RELIABILITY
Endurance7
100
kCycles
Data Retention8
100
Years
1 Typicals represent average readings at 25°C and VDD = 5 V.
2 Guaranteed by design and not subject to production test.
3 See the timing diagrams (Figure 2 and Figure 3) for the location of the measured values. All input control voltages are specified with tR = tF = 2.5 ns (10% to 90% of 3 V)
and timed from a voltage level of 1.5 V. Switching characteristics are measured using both VDD = 3 V and VDD = 5 V.
4 Propagation delay depends on the value of VDD, RPULL-UP, and CL.
5 Valid for commands that do not activate the RDY pin.
6 The RDY pin is low only for Command 2, Command 3, Command 8, Command 9, Command 10, and the PR hardware pulse: CMD_8 > 1 ms; CMD_9, CMD_10 > 0.12 ms;
CMD_2, CMD_3 > 20 ms. Device operation at TA = 40°C and VDD < 3 V extends the save time to 35 ms.
7 Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117, and measured at 40°C, +25°C, and +85°C; typical endurance at 25°C is 700,000 cycles.
8 Retention lifetime equivalent at junction temperature (TJ) = 55°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV
derates with junction temperature, as shown in Figure 45 in the Flash/EEMEM Reliability section.
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