參數(shù)資料
型號(hào)： AD5233BRUZ50-R7
廠商： Analog Devices Inc
文件頁數(shù)： 10/32頁
文件大?。?/td> 0K
描述： IC DGTL POT QUAD 64POS 24-TSSOP
標(biāo)準(zhǔn)包裝： 1,000
接片： 64
電阻（歐姆）： 50k
電路數(shù)： 4
溫度系數(shù)： 標(biāo)準(zhǔn)值 600 ppm/°C
存儲(chǔ)器類型： 非易失
接口： 4 線 SPI（芯片選擇）
電源電壓： 2.7 V ~ 5.5 V，±2.25 V ~ 2.75 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 24-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 24-TSSOP
包裝： 帶卷 (TR)
AD5233
Rev. B | Page 18 of 32
In Table 6, C0 to C3 are command bits, A3 to A0 are address bits, D0 to D5 are data bits that are applicable to the RDAC wiper register,
and D0 to D7 are applicable to the EEMEM register.
Table 6. 16-Bit Serial Data-Word
MSB
Instruction Byte
LSB
Data Byte
RDAC
C3
C2
C1
C0
0
A1
A0
X
D5
D4
D3
D2
D1
D0
EEMEM
C3
C2
C1
C0
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Command instruction codes are defined in Table 7.
Table 7. Instruction/Operation Truth Table1, 2, 3
Inst.
No.
Instruction Byte 0
Data Byte 0
Operation
B16
B8
B7
B6
B5
B4
B3
B2
B1
B0
C3
C2
C1
C0
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
0
X
NOP: Do nothing. See Table 14 for
programming example.
1
0
1
0
A1
A0
X
Restore EEMEM contents to the RDAC
register. This command leaves the device
in read program power state. To return
the part to the idle state, perform NOP
instruction 0. See Table 14.
2
0
1
0
A1
A0
X
Store wiper setting: Store RDAC (ADDR)
setting to EEMEM. See Table 13.
0
1
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Store contents of Serial Register Data
Byte 0 (total eight bits) to EEMEM
(ADDR). See Table 16.
0
1
0
A1
A0
X
Decrement 6 dB: right-shift contents of
RDAC register, stop at all 0s.
0
1
0
1
X
Decrement all 6 dB: right-shift contents
of all RDAC registers, stop at all 0s.
0
1
0
A1
A0
X
Decrement content of RDAC register
by 1, stop at all 0s.
0
1
X
Decrement contents of all the RDAC
registers by 1, stop at all 0s.
8
1
0
X
Reset: refresh all RDACs with their
corresponding EEMEM previously
stored values.
9
1
0
1
A3
A2
A1
A0
X
Read content of EEMEM (ADDR) from
SDO output in the next frame. See
10
1
0
1
0
A1
A0
X
Read RDAC wiper setting from SDO
output in the next frame. See Table 18.
11
1
0
1
0
A1
A0
X
D5
D4
D3
D2
D1
D0
Write contents of Serial Register Data
Byte 0 (total six bits) to RDAC. See
1
0
A1
A0
X
Increment 6 dB: Left-shift contents of
RDAC register, stop at all 1s. See
1
0
1
X
Increment all 6 dB: left-shift contents of
RDAC registers, stop at all 1s.
1
0
A1
A0
X
Increment contents of the RDAC
register by 1, stop at all 1s. See
1
X
Increment contents of all RDAC
registers by 1, stop at all 1s.
1 The SDO output shifts out the last 16 bits of data clocked into the serial register for daisy-chain operation. Exception: for any instruction following Instruction 9 or
Instruction 10, see details of these instructions for proper usage.
2 The RDAC register is a volatile scratchpad register that is automatically refreshed at power-on from the corresponding nonvolatile EEMEM register.
3 Execution of these operations takes place when the CS strobe returns to Logic 1.
4 Instruction 3 writes one data byte (eight bits of data) to EEMEM. In the case of Address 0, Address 1, Address 2, and Address 3, only the last six bits are valid for wiper
position setting.
5 The increment, decrement, and shift instructions ignore the contents of the Shift Register Data Byte 0.
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