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參數(shù)資料
| 型號： | AD5233BRUZ50-R7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 31/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DGTL POT QUAD 64POS 24-TSSOP |
| 標準包裝： | 1,000 |
| 接片： | 64 |
| 電阻（歐姆）： | 50k |
| 電路數(shù)： | 4 |
| 溫度系數(shù)： | 標準值 600 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | 4 線 SPI（芯片選擇） |
| 電源電壓： | 2.7 V ~ 5.5 V，±2.25 V ~ 2.75 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 24-TSSOP |
| 包裝： | 帶卷 (TR) |
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AD5233
Rev. B | Page 8 of 32
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
CLK
SDI
SDO
VSS
GND
A1
RDY
VDD
A4
W4
O1
W1
O2
B4
B1
A3
A2
W3
W2
B3
B2
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
AD5233
TOP VIEW
(Not to Scale)
CS
PR
WP
02
79
4-
0
05
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
O1
Nonvolatile Digital Output 1. Address (O1) = 0x4, the data bit position is D0; defaults to Logic 1 initially.
2
CLK
Serial Input Register Clock Pin. Shifts in one bit at a time on positive clock edges.
3
SDI
Serial Data Input Pin. Shifts in one bit at a time on positive CLK edges. MSB loaded first.
4
SDO
Serial Data Output Pin. Serves readback and daisy-chain functions.
Command 9 and Command 10 activate the SDO output for the readback function, delayed by 16 or 17 clock
pulses, depending on the clock polarity before and after the data-word (see Figure 2, Figure 3, and Table 7).
In other commands, the SDO shifts out the previously loaded SDI bit pattern, delayed by 16 or 17 clock pulses,
depending on the clock polarity (see Figure 2 and Figure 3). This previously shifted-out SDI can be used for daisy-
chaining multiple devices.
Whenever SDO is used, a pull-up resistor in the range of 1 kΩ to 10 kΩ is needed.
5
GND
Ground Pin, Logic Ground Reference.
6
VSS
Negative Supply. Connect to 0 V for single-supply applications. If VSS is used in dual supply, it must be able to sink
40 mA for 25 ms when storing data to EEMEM.
7
A1
Terminal A of RDAC1.
8
W1
Wiper Terminal of RDAC1, Address (RDAC1) = 0x0.
9
B1
Terminal B of RDAC1.
10
A2
Terminal A of RDAC2.
11
W2
Wiper Terminal of RDAC2, Address (RDAC2) = 0x1.
12
B2
Terminal B of RDAC2.
13
B3
Terminal B of RDAC3.
14
W3
Wiper Terminal of RDAC3, Address (RDAC3) = 0x2.
15
A3
Terminal A of RDAC3.
16
B4
Terminal B of RDAC4.
17
W4
Wiper Terminal of RDAC4, Address (RDAC4) = 0x3.
18
A4
Terminal A of RDAC4.
19
VDD
Positive Power Supply Pin.
20
WP
Optional Write Protect Pin. When active low, WP prevents any changes to the present contents, except PR strobe
and Instruction 1 and Instruction 8, and refreshes the RDAC register from EEMEM. Execute a NOP instruction
before returning to WP high. Tie WP to VDD if not used.
21
PR
Optional Hardware Override Preset Pin. Refreshes the scratchpad register with current contents of the EEMEM
register. Factory default loads midscale 0x20 until EEMEM is loaded with a new value by the user. PR is activated at
the Logic 1 transition. Tie PR to VDD if not used.
22
CS
Serial Register Chip Select Active Low. Serial register operation takes place when CS returns to Logic 1.
23
RDY
Ready. Active-high open-drain output. Identifies completion of Software Instruction 2, Software Instruction 3,
Software Instruction 8, Software Instruction 9, Software Instruction 10, and Hardware Instruction PR.
24
O2
Nonvolatile Digital Output 2. Address (O2) = 0x4, the data bit position is D1; defaults to Logic 1 initially.
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