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參數(shù)資料
| 型號(hào)： | AD1954YSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 4/36頁(yè) |
| 文件大小： | 0K |
| 描述： | IC DAC AUDIO 3CHAN 26BIT 48LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | SigmaDSP® |
| 位數(shù)： | 26 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 3 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 510mW |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 托盤(pán) |
| 輸出數(shù)目和類型： | 6 電壓，單極 |
| 采樣率（每秒）： | 48k |
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AD1954
–12–
SIGNAL PROCESSING
Signal Processing Overview
Figure 2 shows the signal processing flow diagram of the AD1954.
The AD1954 is designed to provide all the signal processing
functions commonly used in 2.0 or 2.1 playback systems. A seven-
biquad equalizer operates on the stereo input signal.The output of
this equalizer is fed to a two-biquad crossover filter for the main
channels, and the mono sum of the left and right equalizer outputs
is fed to a three-biquad crossover filter for the subchannel. Each
of the three channels has independent delay compensation.There
are two high quality compressor/limiters available: one operating
on the left/right outputs and one operating on the subwoofer chan-
nel.The subwoofer output may be blended back into the left/right
outputs for 2.0 playback systems. In this configuration, the two
independent compressor/limiters provide two-band compression,
which significantly improves the sound quality of compressed
audio. In addition, the main channels have a stereo widening
algorithm that increases the perceived spread of the stereo image.
Most of the signal processing functions are coded using full 48-bit
double-precision arithmetic.The input word length is 24 bits, with
two extra headroom bits added in the processor to allow internal
gains up to 12 dB without clipping (additional gains can be
accommodated by scaling down the input signal in the first biquad
filter section).
A graphical user interface (GUI) is available for evaluation of
the AD1954 (Figure 3).This GUI controls all of the functions of
the chip in a very straightforward and user friendly interface. No
code needs to be written to use the GUI to control the chip. For
more information on AD1954 software tools, send an e-mail to
SigmaDSP@analog.com.
Each section of this flow diagram will be explained in detail on
the following pages.
Numeric Formats
It is common in DSP systems to use a standardized method of
specifying numeric formats.To better comprehend issues relating to
precision and overflow, it is helpful to think in terms of fractional
twos complement number systems. Fractional number systems
are specified by an A.B format, where A is the number of bits to
the left of the decimal point, and B is the number of bits to the
right of the decimal point. In a twos complement system, there is
also an implied offset of one-half of the binary range; for example,
in a twos complement 1.23 system, the legal signal range is
–1.0 to +(1.0 – 1 LSB).
The AD1954 uses two different numeric formats: one for the
coefficient values (stored in the parameter RAM) and one for the
signal data values.The coefficient format is as follows:
Coefficient Format
Coefficient Format: 2.20
Range: –2.0 to +(2.0 – 1 LSB)
Examples:
1000000000000000000000 = –2.0
1100000000000000000000 = –1.0
1111111111111111111111 = (1 LSB below 0.0)
0000000000000000000000 = 0.0
0100000000000000000000 = 1.0
0111111111111111111111 = (2.0 – 1 LSB)
This format is used because standard biquad filters require
coefficients that range between +2.0 and –2.0. It also allows gain
to be inserted at various places in the signal path.
Internal DSP Signal Data Format
Input Data Format: 1.23
This is sign extended when written to the data memory of the
AD1954.
Internal DSP Signal Data Format: 3.23
Range: –4.0 to +(4.0 – 1 LSB)
Examples:
10000000000000000000000000 = –4.0
11000000000000000000000000 = –2.0
11100000000000000000000000 = –1.0
11111111111111111111111111 = (1 LSB below 0.0)
00000000000000000000000000 = 0.0
00100000000000000000000000 = 1.0
01000000000000000000000000 = 2.0
01111111111111111111111111 = (4.0 – 1 LSB).
The sign extension between the serial port and the DSP core
allows for up to 12 dB of gain in the signal path without internal
clipping. Gains greater than 12 dB can be accommodated by
scaling the input down in the first biquad filter and scaling the
signal back up at the end of the biquad filter section.
A digital clipper circuit is used between the output of the DSP
core and the input to the DAC - modulators to prevent over-
loading the DAC circuitry (see Figure 4). Note that there is a gain
factor of 0.75 used in the DAC interpolation filters, and therefore
signal values of up to 1/0.75 will pass through the DSP without
clipping. Since the DAC is designed to produce an analog output
of 2 V rms (differential) with a 0 dB digital input, signals between
HPF/
DEEMPH
HPF/
DEEMPH
IN
RIGHT
IN
LEFT
VOLUME
PHAT
STEREO
DELAY
(0ms–3.7ms)
DELAY
(0ms–3.7ms)
DELAY
(0ms–2.3ms)
DELAY
(0ms–2.3ms)
8
INTERPOLATION
DAC
OUT
LEFT
8
INTERPOLATION
DAC
OUT
RIGHT
VOLUME
1 BIQUAD
FILTER
DELAY
(0ms–3.7ms)
MONO DAC
L/R REINJECTION
LEVEL
SUBWOOFER
OUTPUT
SUB DYNAMICS PROCESSOR
SUB CHANNEL
L/R MIX
EQ AND CROSSOVER FILTERS
L/R DYNAMICS PROCESSOR
LEVEL DETECT,
LOOK-UP TABLE
LEVEL DETECT,
LOOK-UP TABLE
7 BIQUAD
FILTERS
7 BIQUAD
FILTERS
CROSSOVER
(2 FILTERS)
CROSSOVER
(2 FILTERS)
CROSSOVER
(3 FILTERS)
Figure 2. Signal Processing Flow
REV. A
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| AD1954YSTZRL | 功能描述:IC DAC AUDIO 3CHAN 26BIT 48LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:SigmaDSP® 標(biāo)準(zhǔn)包裝:47 系列:- 設(shè)置時(shí)間:2µs 位數(shù):14 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:55µW 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:管件 輸出數(shù)目和類型:1 電流，單極；1 電流，雙極 采樣率（每秒）:* |
| AD1954YSZ | 制造商:Analog Devices 功能描述:DAC 3-CH Delta-Sigma 24-bit 44-Pin MQFP |
| AD1955 | 制造商:AD 制造商全稱:Analog Devices 功能描述:High Performance Multibit DAC with SACD Playback |
| AD1955ARS | 制造商:Rochester Electronics LLC 功能描述:24 BIT 192KHZ DAC 123 DB DNR WITH SACD - Bulk 制造商:Analog Devices 功能描述:IC DAC 24-BIT |
| AD1955ARSRL | 制造商:Analog Devices 功能描述:DAC 2-CH Delta-Sigma 24-bit 28-Pin SSOP T/R 制造商:Rochester Electronics LLC 功能描述:24 BIT 192KHZ DAC 123 DB DNR WITH SACD - Bulk |
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