參數(shù)資料
型號： AD1954YSTZ
廠商： Analog Devices Inc
文件頁數(shù)： 14/36頁
文件大小： 0K
描述： IC DAC AUDIO 3CHAN 26BIT 48LQFP
產(chǎn)品培訓模塊： Data Converter Fundamentals
DAC Architectures
標準包裝： 1
系列： SigmaDSP®
位數(shù)： 26
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 3
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 510mW
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應商設備封裝： 48-LQFP（7x7）
包裝： 托盤
輸出數(shù)目和類型： 6 電壓，單極
采樣率（每秒）： 48k
AD1954
–21–
The initiate-safe-transfer Bit 9 will request a data transfer from
the SPI safeload registers to the parameter RAM.The safeload
registers contain address-data pairs, and only those registers
that have been written to since the last transfer operation will be
uploaded.The user may poll for this operation to complete by
reading Bit 0 of Control Register 1.The Safeload Mechanism
section goes into more detail on this feature.
Bit 10, the halt program bit, is used to initiate a volume ramp-down
followed by a shutdown of the DSP core.The user may poll for
this operation to complete by reading Bit 1 of Control Register 1.
Bit 11 sets the function of the de-emphasis/auxiliary serial input
pin.When this bit is set to 1, the pin will function as an auxiliary
serial input that is clocked by the input mux’s selected clocks.
When set to 0, this pin enables the 44.1 kHz de-emphasis curve.
Table III. Control Register 1 Write Definition
Register Bits
Function
11
De-emphasis/Auxiliary Serial Input Pin Select
(1 = Auxiliary Serial Input)
10
Halt Program (1 = Halt)
9
Initiate Safe Transfer (1 = Transfer)
8
Enable DCSOUT Output Pin (1 = Enable)
7
Soft Mute (1 = Start Mute Sequence)
6
Soft Power-Down (1 = Power-Down)
5:4
De-emphasis Curve Select
00 = None
01 = 44.1 kHz
10 = 32 kHz
11 = 48 kHz
3:2
Serial in Mode
00 = I2S
01 = Right-Justified
10 = DSP
11 = Left-Justified
1:0
Word Length
00 = 24 Bits
01 = 20 Bits
10 = 16 Bits
11 = 16 Bits
Table IV. Control Register 1 Read Definition
Register Bits
Function
1
DSP Core Shutdown Complete
1 = Shutdown Complete
0 = Not Shut Down
0
Safe Memory Load Complete
1 = Complete (Note: Cleared after Read)
0 = Not Complete
Bit 0 is asserted when all requested safeload registers have been
transferred to the parameter RAM. It is cleared after the read
operation is complete.
Bit 1 is asserted after the requested shutdown of the DSP is com-
pleted.When this bit is set, the user is free to write or read any
RAM location without causing an audio pop or click.
Table V. Control Register 2 Write Definition
Register Bits
Function
9
Volume Ramp Speed
1 = 160 ms Full Ramp Time
0 = 20 ms Full Ramp Time
8
Serial Port Output Enable
1 = Enabled
0 = Disabled
7:6
Serial Port Input Select
00 = IN0
01 = IN1
10 = IN2
11 = NA
5:4
MCLK Input Select
00 = MCLK0
01 = MCLK1
10 = MCLK2
11 = NA
3
Reserved
2
MCLK in Frequency Select
0 = 512 fS
ff
1 = 256 fS
ff
1:0
MCLK Out Frequency Select
00 = Disabled
01 = 512 fS
ff
10 = 256 fS
ff
11 = MCLK_Out = MCLK_In (Feedthrough)
Control Register 2
TableV documents the contents of Control Register 2. Bits 1 and 0
set the frequency of the MCLKOUT pin. If these bits are set to
00, then the MCLKOUT pin is disabled (default).When set to
01, the MCLKOUT pin is set to 512 fS
ff , which is the same as
the internal master clock used by the DSP core.When set to 10,
this pin is set to 256 fS
ff , derived by dividing the internal DSP
clock by 2. In this mode, the output 256 fS
clock by 2. In this mode, the output 256 f
clock by 2. In this mode, the output 256 f clock will be inverted
with respect to the input 256 fS
with respect to the input 256 f
with respect to the input 256 f clock.This is not the case with the
feedthrough mode.When set to 11, the MCLKOUT pin mirrors
the selected MCLK input pin (it’s the output of the MCLK mux
selector). Note that the internal DSP master clock may either be
the same as the selected MCLK pin (when MCLK frequency
select is set to 512 fS
ff mode) or may be derived from the MCLK
pin using an internal clock doubler (when MCLK frequency
select is set to 256 fS
ff ).
Bit 2 selects one of two possible MCLK input frequencies.When
set to 0 (default), the MCLK frequency is set to 512 fS
ff . In this
mode, the internal DSP clock and the external MCLK are at the
same frequency.When set to 1, the MCLK frequency is set to
256 fS
ff , and an internal clock doubler is used to generate the
DSP clock.
Bits 5 and 4 select one of three clock input sources using an inter-
nal mux.To avoid click and pop noises when switching MCLK
sources, it is recommended that the user put the DSP core in
shutdown before switching MCLK sources.
Bits 7 and 6 select one of three serial input sources using an
internal mux. Each source selection includes a separate SDATA,
LRCLK, and BCLK input.To avoid click and pop noises when
switching serial sources, it is recommended that the user put the
DSP core in shutdown before writing to these bits.
REV. A
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD1954YSTZRL 功能描述:IC DAC AUDIO 3CHAN 26BIT 48LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:SigmaDSP® 標準包裝:47 系列:- 設置時間:2µs 位數(shù):14 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:55µW 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應商設備封裝:28-SSOP 包裝:管件 輸出數(shù)目和類型:1 電流，單極；1 電流，雙極 采樣率（每秒）:*
AD1954YSZ 制造商:Analog Devices 功能描述:DAC 3-CH Delta-Sigma 24-bit 44-Pin MQFP
AD1955 制造商:AD 制造商全稱:Analog Devices 功能描述:High Performance Multibit DAC with SACD Playback
AD1955ARS 制造商:Rochester Electronics LLC 功能描述:24 BIT 192KHZ DAC 123 DB DNR WITH SACD - Bulk 制造商:Analog Devices 功能描述:IC DAC 24-BIT
AD1955ARSRL 制造商:Analog Devices 功能描述:DAC 2-CH Delta-Sigma 24-bit 28-Pin SSOP T/R 制造商:Rochester Electronics LLC 功能描述:24 BIT 192KHZ DAC 123 DB DNR WITH SACD - Bulk
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