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參數(shù)資料
| 型號： | AD14160L |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Quad-SHARC DSP Multiprocessor Family |
| 中文描述： | 四SHARC處理器DSP的多處理器家族 |
| 文件頁數(shù)： | 41/52頁 |
| 文件大?。?/td> | 1193K |
| 代理商： | AD14160L |
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AD14160/AD14160L
–41–
REV. A
GROUND BOUNCE ESTIMATE
Ground bounce diminishes noise margins in a system and must
be held as low as possible. Ground bounce results from switch-
ing output pins from a high to a low state with the ensuing dis-
charge current creating a voltage across the parasitic inductance
of the MCM’s ground pins (and to a lesser extent across the
wirebond wires connecting the ground pads). A useful model for
calculating the level of ground bounce is shown below (Johnson,
Howard W. and Graham, Martin, “High-Speed Digital Design,”
Prentice Hall p67, 1993).
GROUND PIN
INDUCTANCE
L
GND
V
IN
V
DD
SHARC DIE
LOAD C
I
DISCHARGE
V
GND
SYSTEM GROUND PLANE
Figure 40.
In the Quad-SHARC module, the worse case ground bounce
condition occurs during an external memory operation in which
86 signals switch simultaneously from high to low. Because of
the ground planes embedded within the substrate of the mod-
ule, the effective ground pin inductance is found by dividing the
CBGA’s single ground pin inductance, estimated to be about
3 nH, by the 64 ground pins resulting in L
GND
= 0.05 nH.
Typical output fall times for varying load conditions can be
obtained from this data sheet.
The induced voltage generated by the switching currents is
given by
V
GND
=
L
GND
d
dt
(
I
DISCHARGE
)
Assuming the voltage waveform is an integrated Gaussian pulse,
the peak amplitude is approximated by
|
V
GND
|
max
= L
GND
1.52
V
T
10–902
C
.
Calculated ground bounce maximum values for the CBGA
module are listed below.
Load per Output
(pF)
Fall Time
(ns)
Ground Bounce
(V)
20
100
200
1.8
4.2
7.4
0.161
0.148
0.095
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