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參數(shù)資料
| 型號： | AD14160L |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Quad-SHARC DSP Multiprocessor Family |
| 中文描述： | 四SHARC處理器DSP的多處理器家族 |
| 文件頁數(shù)： | 27/52頁 |
| 文件大小： | 1193K |
| 代理商： | AD14160L |
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AD14160/AD14160L
–27–
REV. A
40 MHz–5 V
40 MHz–3.3 V
Min
Parameter
Min
Max
Max
Units
Timing Requirements:
t
STSCK
t
HTSCK
SBTS
Setup Before CLKIN
SBTS
Hold Before CLKIN
12 + DT/2
12 + DT/2
ns
ns
6 + DT/2
6 + DT/2
Switching Characteristics:
t
MIENA
t
MIENS
t
MIENHG
t
MITRA
t
MITRS
t
MITRHG
t
DATEN
t
DATTR
t
ACKEN
t
ACKTR
t
ADCEN
t
ADCTR
t
MTRHBG
t
MENHBG
Address/Select Enable After CLKIN
Strobes Enable After CLKIN
1
HBG
Enable After CLKIN
Address/Select Disable After CLKIN
Strobes Disable After CLKIN
1
HBG
Disable After CLKIN
Data Enable After CLKIN
2
Data Disable After CLKIN
2
ACK Enable After CLKIN
2
ACK Disable After CLKIN
2
ADRCLK Enable After CLKIN
ADRCLK Disable After CLKIN
Memory Interface Disable Before
HBG
Low
3
Memory Interface Enable After
HBG
High
3
–1.5 – DT/8
–1.5 – DT/8
–1.5 – DT/8
–1.25 – DT/8
–1.5 – DT/8
–1.5 – DT/8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1 – DT/4
2.5 – DT/4
2.5 – DT/4
1 – DT/4
2.5 – DT/4
2.5 – DT/4
9 + 5DT/16
0 – DT/8
7.5 + DT/4
–1 – DT/8
–2 – DT/8
9 + 5DT/16
0 – DT/8
7.5 + DT/4
–1 – DT/8
–2 – DT/8
8 – DT/8
8 – DT/8
7 – DT/8
7 – DT/8
8.5 – DT/4
8.5 – DT/4
–0.5 + DT/8
18.5 + DT
–0.5 + DT/8
18.5 + DT
NOTES
1
Strobes =
RD
,
WR
,
SW
, PAGE,
DMAG
.
2
In addition to bus master transition cycles, these specs also apply to bus master and bus slave synchronous read/write.
3
Memory Interface = Address,
RD
,
WR
,
MS
x,
SW
,
HBG
, PAGE,
DMAGx
,
BMS
(in EPROM boot mode).
CLKIN
ACK
MEMORY
INTERFACE
t
MENHBG
t
MTRHBG
HBG
MEMORY INTERFACE = ADDRESS,
RD
,
WR
,
MS
x,
SW
,
HBG
, PAGE,
DMAG
x.
BMS
(IN EPROM BOOT MODE)
t
MITRA,
t
MITRS,
t
MITRHG
t
STSCK
t
HTSCK
t
DATTR
t
DATEN
t
ACKTR
t
ACKEN
t
ADCTR
t
ADCEN
ADRCLK
DATA
t
MIENA,
t
MIENS,
t
MIENHG
MEMORY
INTERFACE
Figure 20. Three-State Timing
Three-State Timing—Bus Master, Bus Slave,
HBR
,
SBTS
These specifications show how the memory interface is disabled
(stops driving) or enabled (resumes driving) relative to CLKIN
and the
SBTS
pin. This timing is applicable to bus master tran-
sition cycles (BTC) and host transition cycles (HTC) as well as
the
SBTS
pin.
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