參數(shù)資料
型號(hào)： AD14160L
廠商： Analog Devices, Inc.
英文描述： Quad-SHARC DSP Multiprocessor Family
中文描述： 四SHARC處理器DSP的多處理器家族
文件頁(yè)數(shù)： 12/52頁(yè)
文件大?。?/td> 1193K
代理商： AD14160L
AD14160/AD14160L
–12–
REV. A
TARGET BOARD CONNECTOR FOR EZ-ICE PROBE
The ADSP-2106x EZ-ICE Emulator uses the IEEE 1149.1
JTAG test access port of the ADSP-2106x to monitor and con-
trol the target board processor during emulation. The EZ-ICE
probe requires that the AD14160/AD14160L’s CLKIN (op-
tional), TMS, TCK,
TRST
, TDI, TDO,
EMU
and GND signals
be made accessible on the target system via a 14-pin connector
(a pin strip header) such as that shown in Figure 6. The EZ-
ICE probe plugs directly onto this connector for chip-on-board
emulation. You must add this connector to your target board
design if you intend to use the ADSP-2106x EZ-ICE. The
length of the traces between the connector and the AD14160/
AD14160L’s JTAG pins should be as short as possible.
TOP VIEW
13
14
11
12
9
10
9
7
8
5
6
3
4
1
2
EMU
CLKIN (OPTIONAL)
TMS
TCK
TRST
TDI
TDO
GND
KEY (NO PIN)
BTMS
BTCK
BTRST
BTDI
GND
Figure 6. Target Board Connector for ADSP-2106x EZ-ICE
Emulator (Jumpers in Place)
The 14-pin, 2-row pin strip header is keyed at the Pin 3 location;
Pin 3 must be removed from the header. The pins must be
0.025 inch square and at least 0.20 inch in length. Pin spacing
should be 0.1
×
0.1 inches. Pin strip headers are available from
vendors such as 3M, McKenzie and Samtec.
The BTMS, BTCK,
BTRST
and BTDI signals are provided so
that the test access port can also be used for board-level testing.
When the connector is not being used for emulation, place
jumpers between the Bxxx pins and the xxx pins as shown in
Figure 6. If you are not going to use the test access port for
board testing, tie
BTRST
to GND and tie or pull up BTCK to
V
DD
. The
TRST
pin must be asserted after power-up (through
BTRST
on the connector) or held low for proper operation of
the AD14160/AD14160L. None of the Bxxx pins (Pins 5, 7, 9,
11) are connected on the EZ-ICE probe.
The JTAG signals are terminated on the EZ-ICE probe as follows:
Signal
Termination
Driven through 22
Resistor (16 mA/3.2 mA Driver)
Driven at 10 MHz through 22
Resistor (16 mA/
3.2 mA Driver)
Driven by Open-Drain Driver* (Pulled Up by On-Chip
20 k
Resistor)
Driven by 16 mA/3.2 mA Driver
One TTL Load, No Termination
One TTL Load, No Termination (Optional Signal)
4.7 k
Pull-Up Resistor, One TTL Load (Open-Drain
Output from ADSP-2106x)
TMS
TCK
TRST
TDI
TDO
CLKIN
EMU
*
TRST
is driven low until the EZ-ICE probe is turned on by the EZ-ICE
software (after the invocation command).
Figure 7 shows JTAG scan path connections for the multi-
processor system.
SHARC_A
TDI
TDO
T
T
E
T
EZ-ICE
JTAG
CONNECTOR
TDI
TCK
TMS
EMU
TRST
TDO
CLKIN
OTHER
JTAG
CONTROLLER
SHARC_B
TDI
TDO
T
T
E
T
SHARC_C
TDI
TDO
T
T
E
T
SHARC_D
TDI
TDO
T
T
E
T
JTAG DEVICE
(OPTIONAL)
TDI
TDO
T
T
T
TDI
TDO
T
T
E
T
ADSP-2106x
#n
OPTIONAL
Figure 7. JTAG Scan Path Connections for the AD14160/AD14160L
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