參數(shù)資料
型號(hào)： AD14160BB-4
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號(hào)處理
英文描述： Quad-SHARC DSP Multiprocessor Family
中文描述： 48-BIT, 40 MHz, OTHER DSP, CBGA452
封裝： CERAMIC, BGA-452
文件頁(yè)數(shù)： 33/52頁(yè)
文件大小： 1193K
代理商： AD14160BB-4
AD14160/AD14160L
–33–
REV. A
Serial Ports
40 MHz–5 V
40 MHz–3.3 V
Min
Parameter
Min
Max
Max
Units
External Clock
Timing Requirements:
t
SFSE
t
HFSE
t
SDRE
t
HDRE
t
SCLKW
t
SCLK
TFS/RFS Setup Before TCLK/RCLK
1
TFS/RFS Hold After TCLK/RCLK
1, 2
Receive Data Setup Before RCLK
1
Receive Data Hold After RCLK
1
TCLK/RCLK Width
TCLK/RCLK Period
3.5
4
1.5
4
9.5
t
CK
3.5
4
1.5
4
9
t
CK
ns
ns
ns
ns
ns
ns
Internal Clock
Timing Requirements:
t
SFSI
t
HFSI
t
SDRI
t
HDRI
TFS Setup Before TCLK
1
; RFS Setup Before RCLK
1
8
TFS/RFS Hold After TCLK/RCLK
1, 2
Receive Data Setup Before RCLK
1
Receive Data Hold After RCLK
1
8
1
3
3
ns
ns
ns
ns
1
3
3
External or Internal Clock
Switching Characteristics:
t
DFSE
RFS Delay After RCLK (Internally Generated RFS)
3
t
HFSE
RFS Hold After RCLK (Internally Generated RFS)
3
13.5
13.5
ns
ns
3
3
External Clock
Switching Characteristics:
t
DFSE
TFS Delay After TCLK (Internally Generated TFS)
3
t
HFSE
TFS Hold After TCLK (Internally Generated TFS)
3
t
DDTE
Transmit Data Delay After TCLK
3
t
HDTE
Transmit Data Hold After TCLK
3
13.5
13.5
ns
ns
ns
ns
3
3
16.5
16.5
5
5
Internal Clock
Switching Characteristics:
t
DFSI
TFS Delay After TCLK (Internally Generated TFS)
3
t
HFSI
TFS Hold After TCLK (Internally Generated TFS)
3
t
DDTI
Transmit Data Delay After TCLK
3
t
HDTI
Transmit Data Hold After TCLK
3
t
SCLKIW
TCLK/RCLK Width
4.5
4.5
ns
ns
ns
ns
ns
–1.5
–1.5
7.5
7.5
0
(SCLK/2) – 2
0
(SCLK/2) – 2.5
(SCLK/2) + 2
(SCLK/2) + 2.5
Enable and Three-State
Switching Characteristics:
t
DDTEN
Data Enable from External TCLK
3
t
DDTTE
Data Disable from External TCLK
3
t
DDTIN
Data Enable from Internal TCLK
3
t
DDTTI
Data Disable from Internal TCLK
3
t
DCLK
TCLK/RCLK Delay from CLKIN
t
DPTR
SPORT Disable After CLKIN
3.5
4
ns
ns
ns
ns
ns
ns
11
11
0
0
3
22.5 + 3DT/8
17.5
3
22.5 + 3DT/8
17.5
External Late Frame Sync
Switching Characteristics:
t
DDTLFSE
Data Delay from Late External TFS or
External RFS with MCE = 1, MFD = 0
4
t
DDTENFS
Data Enable from Late FS or MCE = 1, MFD = 0
4
12.5
13.3
ns
3
3.5
ns
To determine whether communication is possible between two devices at clock speed
n,
the following specifications must be confirmed: 1) frame sync delay and frame
sync setup and hold, 2) data delay and data setup and hold, and 3) SCLK width.
NOTES
1
Referenced to sample edge.
2
RFS hold after RCK when MCE = 1, MFD = 0 is 0 ns minimum from drive edge. TFS hold after TCK for late external TFS is 0 ns minimum from drive edge.
3
Referenced to drive edge.
4
MCE = 1, TFS enable and TFS valid follow t
DDTLFSE
and t
DDTENFS
.
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