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參數(shù)資料
| 型號： | AD14160BB-4 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Quad-SHARC DSP Multiprocessor Family |
| 中文描述： | 48-BIT, 40 MHz, OTHER DSP, CBGA452 |
| 封裝： | CERAMIC, BGA-452 |
| 文件頁數(shù)： | 28/52頁 |
| 文件大小： | 1193K |
| 代理商： | AD14160BB-4 |
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AD14160/AD14160L
–28–
REV. A
transfer is controlled by ADDR
31-0
,
RD
,
WR
,
MS
3-0
, and ACK
(not
DMAG
). For Paced Master mode, the “Memory Read–Bus
Master”, “Memory Write–Bus Master”, and “Synchronous
Read/Write–Bus Master” timing specifications for ADDR
31-0
,
RD
,
WR
,
MS
3-0
,
SW
, PAGE, DATA
47-0
, and ACK also apply.
40 MHz–5 V
40 MHz–3.3 V
Min
Parameter
Min
Max
Max
Units
Timing Requirements:
t
SDRLC
t
SDRHC
t
WDR
t
SDATDGL
t
HDATIDG
t
DATDRH
t
DMARLL
t
DMARH
DMAR
x Low Setup Before CLKIN
1
DMAR
x High Setup Before CLKIN
1
DMAR
x Width Low (Nonsynchronous)
Data Setup After
DMAG
x Low
2
Data Hold After
DMAG
x High
Data Valid After
DMAG
x High
2
DMAG
x Low Edge to Low Edge
DMAG
x Width High
5.5
5.5
6
5.5
5.5
6
ns
ns
ns
ns
ns
ns
ns
ns
9 + 5DT/8
9 + 5DT/8
2.5
2.5
15 + 7DT/8
15 + 7DT/8
23 + 7DT/8
6
23 + 7DT/8
6
Switching Characteristics:
t
DDGL
t
WDGH
t
WDGL
t
HDGC
t
VDATDGH
t
DATRDGH
t
DGWRF
t
DGWRH
t
DGWRR
t
DGRDF
t
DRDGH
t
DGRDR
t
DGWR
t
DADGH
t
DDGHA
DMAG
x Low Delay After CLKIN
DMAG
x High Width
DMAG
x Low Width
DMAG
x High Delay After CLKIN
Data Valid Before
DMAG
x High
3
Data Disable After
DMAG
x High
4
WR
Low Before
DMAG
x Low
DMAG
x Low Before
WR
High
WR
High Before
DMAG
x High
RD
Low Before
DMAG
x Low
RD
Low Before
DMAG
x High
RD
High Before
DMAG
x High
DMAG
x High to
WR
,
RD
,
DMAG
x Low
Address/Select Valid to
DMAG
x High
Address/Select Hold After
DMAG
x High
9 + DT/4
6 + 3DT/8
12 + 5DT/8
–2 – DT/8
7 + 9DT/16
–0.5
–0.5
9.5 + 5DT/8 + W
0.5 + DT/16
–0.5
10.5 + 9DT/16 + W
–0.5
5 + 3DT/8 + HI
16 + DT
–1.5
16 + DT/4
9 + DT/4
6 + 3DT/8
12 + 5DT/8
–2 – DT/8
7 + 9DT/16
–0.5
–0.5
9.5 + 5DT/8 + W
0.5 + DT/16
–0.5
10.5 + 9DT/16 + W
–0.5
5 + 3DT/8 + HI
16 + DT
–1.5
16 + DT/4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7 – DT/8
7 – DT/8
8
2.5
8
2.5
3.5 + DT/16
2.5
3.5 + DT/16
2.5
3.5
3.5
W = (number of wait states specified in WAIT register)
×
t
CK
.
HI = t
CK
(if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
NOTES
1
Only required for recognition in the current cycle.
2
t
SDATDGL
is the data setup requirement if
DMAR
x is not being used to hold off completion of a write. Otherwise, if
DMAR
x low holds off completion of the write, the
data can be driven t
DATDRH
after
DMAR
x is brought high.
3
t
VDATDGH
is valid if
DMAR
x is not being used to hold off completion of a read. If
DMAR
x is used to prolong the read, then t
VDATDGH
= 7 + 9DT/16 + (n
×
t
CK
) where
n
equals the number of extra cycles that the access is prolonged.
4
See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
DMA Handshake
These specifications describe the three DMA handshake modes.
In all three modes
DMAR
is used to initiate transfers. For hand-
shake mode,
DMAG
controls the latching or enabling of data
externally. For external handshake mode, the data transfer is
controlled by the ADDR
31-0
,
RD
,
WR
,
SW
, PAGE,
MS
3-0
,
ACK, and
DMAG
signals. For Paced Master mode, the data
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相關(guān)代理商/技術(shù)參數(shù) |
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| AD14160KB-4 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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