參數(shù)資料
型號(hào)： AD14160BB-4
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號(hào)處理
英文描述： Quad-SHARC DSP Multiprocessor Family
中文描述： 48-BIT, 40 MHz, OTHER DSP, CBGA452
封裝： CERAMIC, BGA-452
文件頁數(shù)： 19/52頁
文件大?。?/td> 1193K
代理商： AD14160BB-4
AD14160/AD14160L
–19–
REV. A
40 MHz–5 V
40 MHz–3.3 V
Min
Parameter
Min
Max
Max
Units
Timing Requirements:
t
DAAK
t
DSAK
ACK Delay from Address, Selects
1, 2
ACK Delay from
WR
Low
1
13 + 7DT/8 + W
7 + DT/2 + W
13 + 7DT/8 + W
7 + DT/2 + W
ns
ns
Switching Characteristics:
t
DAWH
t
DAWL
t
WW
t
DDWH
t
DWHA
t
DATRWH
t
WWR
t
DDWR
t
WDE
t
SADADC
Address, Selects to
WR
Deasserted
2
Address, Selects to
WR
Low
2
WR
Pulsewidth
Data Setup Before
WR
High
Address Hold After
WR
Deasserted
Data Disable After
WR
Deasserted
3
WR
High to
WR
,
RD
,
DMAGx
Low
Data Disable Before
WR
or
RD
Low
WR
Low to Data Enabled
Address, Selects to ADRCLK High
2
16 + 15DT/16 + W
2 + 3DT/8
12 + 9DT/16 + W
6 + DT/2 + W
0 + DT/16 + H
0.5 + DT/16 + H
7.5 + 7DT/16 + H
4 + 3DT/8 + I
–1.5 + DT/16
–0.5 + DT/4
16 + 15DT/16 + W
2 + 3DT/8
12 + 9DT/16 + W
6 + DT/2 + W
0 + DT/16 + H
0.5 + DT/16 + H
7.5 + 7DT/16 + H
4 + 3DT/8 + I
–1.5 + DT/16
–0.5 + DT/4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7 + DT/16 + H
7 + DT/16 + H
W = (number of wait states specified in WAIT register)
×
t
CK
.
H = t
CK
(if an address hold cycle occurs, as specified in WAIT register; otherwise H = 0).
I = t
CK
(if a bus idle cycle occurs, as specified in WAIT register; otherwise I = 0).
NOTES
1
ACK Delay/Setup: User must meet t
or t
or synchronous specification t
SACKC
.
2
For
MS
x,
SW
,
BMS
, the falling edge is referenced.
3
See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
RD
,
DMAG
ACK
DATA
WR
ADDRESS
MS
x ,
SW
BMS
t
DAWL
t
WW
t
SADADC
t
DAAK
t
WWR
t
WDE
ADRCLK
(OUT)
t
DDWR
t
DATRWH
t
DWHA
t
DDWH
t
DAWH
t
DSAK
Figure 15. Memory Write—Bus Master
Memory Write—Bus Master
Use these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) without reference to
CLKIN. These specifications apply when the AD14160/
AD14160L is the bus master accessing external memory space.
These switching characteristics also apply for bus master syn-
chronous read/write timing (see Synchronous Read/Write—Bus
Master). If these timing requirements are met, the synchronous
read/write timing can be ignored (and vice versa).
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相關(guān)代理商/技術(shù)參數(shù)
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AD142 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRANSISTOR | BJT | PNP | 80V V(BR)CEO | 10A I(C) | TO-3
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