- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373857 > AD14160BB-4 (ANALOG DEVICES INC) Quad-SHARC DSP Multiprocessor Family PDF資料下載
參數(shù)資料
| 型號： | AD14160BB-4 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Quad-SHARC DSP Multiprocessor Family |
| 中文描述： | 48-BIT, 40 MHz, OTHER DSP, CBGA452 |
| 封裝： | CERAMIC, BGA-452 |
| 文件頁數(shù)： | 10/52頁 |
| 文件大?。?/td> | 1193K |
| 代理商： | AD14160BB-4 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁當(dāng)前第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁
AD14160/AD14160L
–10–
REV. A
Pin
Type
Function
DTy1
O/T
Data Transmit
(Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D) DT pin
has a 50 k
internal pull-up resistor.
Data Receive
(Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D) DR pin
has a 50 k
internal pull-up resistor.
Transmit Clock
(Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D) TCLK
pin has a 50 k
internal pull-up resistor.
Receive Clock
(Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D) RCLK
pin has a 50 k
internal pull-up resistor.
Transmit Frame Sync
(Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D)
Receive Frame Sync
(Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D)
Flag Pins.
(Individual FLAG3-0 from y = SHARC_A, SHARC_B, SHARC_C, SHARC_D) Each is
configured via control bits as either an input or output. As an input, it can be tested as a condition. As an
output, it can be used to signal external peripherals.
Interrupt Request Lines.
(Individual
IRQ
2-0 from y = SHARC_A, SHARC_B, SHARC_C, SHARC_D)
May be either edge-triggered or level-sensitive.
DMA Request 1
(DMA Channel 7). Common to SHARC_A, SHARC_B, SHARC_C, SHARC_D.
DMA Request 2
(DMA Channel 8). Common to SHARC_A, SHARC_B, SHARC_C, SHARC_D.
DMA Grant 1
(DMA Channel 7). Common to SHARC_A, SHARC_B, SHARC_C, SHARC_D.
DMA Grant 2
(DMA Channel 8). Common to SHARC_A, SHARC_B, SHARC_C, SHARC_D.
Link Port Clock
(y = SHARC_A, B, C, D; x = Link Ports 1, 2, 3, 4)
1
. Each LyxCLK pin has a 50 k
internal pull-down resistor which is enabled or disabled by the LPDRD bit of the LCOM register, of the
ADSP-20160.
Link Port Data
(y = SHARC_A, B, C, D; x = Link Ports 1, 2, 3, 4)
1
. Each LyxDAT pin has a
50 k
internal pull-down resistor which is enabled or disabled by the LPDRD bit of the LCOM register,
of the ADSP-21060.
Link Port Acknowledge
(y = SHARC_A, B, C, D; x = Link Ports 1, 2, 3, 4)
1
. Each LyxACK pin has a
50 k
internal pull-down resistor which is enabled or disabled by the LPDRD bit of the LCOM register,
of the ADSP-21060.
EPROM Boot Select.
(SHARC_A) When EBOOTA is high, SHARC_A is configured for booting from
an 8-bit EPROM. When EBOOTA is low, the LBOOTA and
BMSA
inputs determine booting mode for
SHARC_A. See the following table. This signal is a system configuration selection which should be hardwired.
Link Boot.
When LBOOTA is high, SHARC_A is configured for link port booting. When LBOOTA is
low, SHARC_A is configured for host processor booting or no booting. See the following table. This
signal is a system configuration selection which should be hardwired.
Boot Memory Select.
Output:
Used as chip select for boot EPROM devices (when EBOOTA = 1,
LBOOTA = 0). In a multiprocessor system, BMS is output by the bus master.
Input:
When low, indicates
that no booting will occur and that SHARC_A will begin executing instructions from external memory.
See the following table. This input is a system configuration selection which should be hardwired.
EPROM Boot Select.
(Common to SHARC_B, SHARC_C, SHARC_D) When EBOOTBCD is high,
SHARC_B, C, D are configured for booting from an 8-bit EPROM. When EBOOTBCD is low, the
LBOOTBCD and BMSBCD inputs determine booting mode for SHARC_B, C and D. See the following
table. This signal is a system configuration selection which should be hardwired.
LINK Boot.
(Common to SHARC_B, SHARC_C, SHARC_D) When LBOOTBCD is high, SHARC_B, C,
D are configured for link port booting. When LBOOTBCD is low, SHARC_B, C, D are configured for
host processor booting or no booting. See the following table. This signal is a system configuration selec-
tion which should be hardwired.
DRy1
I
TCLKy1
I/O
RCLKy1
I/O
TFSy1
RFSy1
FLAGy3-0
I/O
I/O
I/O/A
IRQ
y2-0
I/A
DMAR1
DMAR2
DMAG1
DMAG2
LyxCLK
I/A
I/A
O/T
O/T
I/O
LyxDAT3-0
I/O
LyxACK
I/O
EBOOTA
I
LBOOTA
I
BMSA
I/O/T
2
EBOOTBCD
I
LBOOTBCD
I
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD14160L | Quad-SHARC DSP Multiprocessor Family |
| AD14160LBB-4 | ECONOLINE: RD & RC - Dual Output from a Single Input Rail- 1kVDC & 2kVDC Isolation- Power Sharing on Output- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 86% |
| AD14160LKB-4 | Quad-SHARC DSP Multiprocessor Family |
| AD1555-AD1556 | 24-Bit ADC WITH LOW NOISE PGA |
| AD1555AP | 24-Bit ADC WITH LOW NOISE PGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD14160KB-4 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD14160L | 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad-SHARC DSP Multiprocessor Family |
| AD14160LBB-4 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad-SHARC DSP Multiprocessor Family |
| AD14160LKB-4 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD142 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRANSISTOR | BJT | PNP | 80V V(BR)CEO | 10A I(C) | TO-3 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。