參數(shù)資料
型號(hào)： AD14160BB-4
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號(hào)處理
英文描述： Quad-SHARC DSP Multiprocessor Family
中文描述： 48-BIT, 40 MHz, OTHER DSP, CBGA452
封裝： CERAMIC, BGA-452
文件頁數(shù)： 14/52頁
文件大?。?/td> 1193K
代理商： AD14160BB-4
–14–
REV. A
AD14160/AD14160L–SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
B Grade
Min
4.75
3.15
–40
K Grade
Min
4.75
3.15
0
Parameter
V
DD
Max
5.25
3.6
+100
Max
5.25
3.6
+85
Units
V
V
°
C
Supply Voltage (5 V)
Supply Voltage (3.3 V)
Case Operating Temperature
T
CASE
ELECTRICAL CHARACTERISTICS (5 V, 3.3 V SUPPLY)
Case
Temp
Test
Level Test Condition
5 V
3.3 V
Min Typ Max
Parameter
Min Typ Max
Units
V
IH1
V
IH2
V
IL
V
OH
V
OL
I
IH
I
IHX4
I
IL
I
ILX4
I
ILP
I
ILPX4
I
OZH
I
OZHX4
I
OZL
I
OZLX4
I
OZHP
I
OZLC
I
OZLAR
I
OZLA
High Level Input Voltage
1
High Level Input Voltage
2
Low Level Input Voltage
1, 2
High Level Output Voltage
3, 4
Low Level Output Voltage
3, 4
High Level Input Current
5, 6
High Level Input Current
7, 8
Low Level Input Current
5
Low Level Input Current
7
Low Level Input Current
6
Low Level Input Current
8
Three-State Leakage Current
9, 10, 11
Three-State Leakage Current
12
Three-State Leakage Current
9, 13
Three-State Leakage Current
12
Three-State Leakage Current
13
Three-State Leakage Current
14
Three-State Leakage Current
11
Three-State Leakage Current
15
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
@ V
DD
= max
@ V
DD
= max
@ V
DD
= min
@ V
DD
= min, I
OH
= –2.0 mA
4
@ V
DD
= min, I
OL
= 4.0 mA
4
@ V
DD
= max, V
IN
= V
DD
max
@ V
DD
= max, V
IN
= V
DD
max
@ V
DD
= max, V
IN
= 0 V
@ V
DD
= max, V
IN
= 0 V
@ V
DD
= max, V
IN
= 0 V
@ V
DD
= max, V
IN
= 0 V
@ V
DD
= max, V
IN
= V
DD
max
@ V
DD
= max, V
IN
= V
DD
max
@ V
DD
= max, V
IN
= 0 V
@ V
DD
= max, V
IN
= 0 V
@ V
DD
= max, V
IN
= V
DD
max
@ V
DD
= max, V
IN
= 0 V
@ V
DD
= max, V
IN
= 0 V
@ V
DD
= max, V
IN
= 2 V (3.3 V),
1.5 V (5 V)
@ V
= max, V
= 0 V
t
CK
= 25 ns, V
DD
= max
V
DD
= max
2.0
2.2
V
DD
+ 0.5 2.0
V
DD
+ 0.5 2.2
0.8
V
DD
+ 0.5
V
DD
+ 0.5
0.8
V
V
V
V
V
μ
A
μ
A
μ
A
μ
A
μ
A
μ
A
μ
A
μ
A
μ
A
μ
A
μ
A
mA
mA
4.1
2.4
0.4
10
40
10
40
150
600
10
40
10
40
350
1.5
4.2
0.4
10
40
10
40
150
600
10
40
10
40
350
1.5
4.2
350
150
3.4
800
350
150
2.2
760
μ
A
μ
A
A
mA
pF
I
OZLS
I
DDIN
I
DDIDLE
C
IN
Three-State Leakage Current
10
Supply Current (Internal)
16
Supply Current (Idle)
17
Input Capacitance
Full
Full
Full
+25
°
C V
I
IV
I
1.4
1
15
15
EXPLANATION OF TEST LEVELS
Test
Level
I
100% Production Tested
20
.
II
100% Production Tested at +25
°
C, and Sample Tested at Specified Temperatures.
III
Sample Tested Only.
IV
Parameter is guaranteed by design and analysis, and characterization testing on discrete SHARCs.
V
Parameter is typical value only.
VI
All devices are 100% production tested at +25
°
C; sample tested at temperature extremes.
NOTES
Applies to input and bidirectional pins: DATA
, ADDR
31-0
,
RD
,
WR
,
SW
, ACK,
SBTS
,
IRQ
y
2-0
, FLAGy0-3,
HBG
,
CS
y,
DMAR1
,
DMAR2
,
BR
, IDy0-2,
RPBA,
CPA
y, TFSy0, TFSy1, RFSy0, RFSy1, LyxDAT
BMSA
,
BMSBCD
, TMS,
TDI, TCK,
HBR
, DRy0, DRy1, TCLKy0, TCLKy1, RCLKy0, RCLKy1.
2
Applies to input pins: CLKIN,
RESET
,
TRST
.
3
Applies to output and bidirectional pins: DATA
, ADDR
,
MS
RD
,
WR
, PAGE, ADRCLK,
SW
, ACK, FLAGy0-3, TIMEXPy,
HBG
, REDY,
DMAG1
,
DMAG2
,
BR
,
CPA
y, DTy0, DTy1, TCLKy0, TCLKy1, RCLKy0, RCLKy1, TFSy0, TFSy1, RFSy0, RFSy1 LyxDAT
3-0
, LyxCLK, LyxACK,
BMSA
,
BMSBCD
, TDO,
EMU
.
4
See Output Drive Currents for typical drive current capabilities.
5
Applies to input pins:
IRQ
y
,
CS
y, IDy0-2, EBOOTA, LBOOTA.
6
Applies to input pins with internal pull-ups: DRy0, DRy1, TDI.
7
Applies to bussed input pins:
SBTS
,
HBR
,
DMAR1
,
DMAR2
, RPBA, EBOOTBCD, LBOOTBCD, CLKIN,
RESET
, TCK.
8
Applies to bussed input pins with internal pull-ups:
TRST
, TMS.
9
Applies to three-statable pins: FLAGy0-3,
BMSA
, TDO.
10
Applies to three-statable pins with internal pull-ups: DTy0, TCLKy0, RCLKy0, DTy1, TCLKy1, RCLKy1.
11
Applies to ACK pin when pulled up. (Note that ACK is pulled up internally with 2 k
during reset in a multiprocessor system, when ID
2-0
= 001 and another
ADSP-2106x is not requesting bus mastership.)
12
Applies to bussed three-statable pins: DATA
, ADDR
,
MS
,
RD
,
WR
, PAGE, ADRCLK,
SW
, ACK, REDY,
HBG,
DMAG1
,
DMAG2
,
BMSBCD
,
EMU
. (Note
that ACK is pulled up internally with 2 k
during reset in a multiprocessor system, when ID
2-0
= 001 and another ADSP-2106x is not requesting bus mastership.
HBG
and
EMU
are not tested for leakage current.)
相關(guān)PDF資料
PDF描述
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參數(shù)描述
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AD14160L 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad-SHARC DSP Multiprocessor Family
AD14160LBB-4 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad-SHARC DSP Multiprocessor Family
AD14160LKB-4 制造商:Rochester Electronics LLC 功能描述:- Bulk
AD142 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRANSISTOR | BJT | PNP | 80V V(BR)CEO | 10A I(C) | TO-3
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