參數(shù)資料
型號： AD14060BF-4
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號處理
英文描述： Quad-SHARC DSP Multiprocessor Family
中文描述： 48-BIT, 40 MHz, OTHER DSP, CQFP308
封裝： CERAMIC, QFP-308
文件頁數(shù)： 9/44頁
文件大小： 744K
代理商： AD14060BF-4
AD14060/AD14060L
–9–
REV. A
Pin
T ype
Function
SBTS
I/S
Suspend Bus T hree-State.
(Common to all SHARCs) External devices can assert
SBTS
(low) to
place the external bus address, data, selects, and strobes in a high impedance state for the following cycle.
If the AD14060/AD14060L attempts to access external memory while
SBTS
is asserted, the processor
will halt and the memory access will not be completed until
SBTS
is deasserted.
SBTS
should only be
used to recover from host processor/AD14060/AD14060L deadlock, or used with a DRAM controller.
Host Bus Request.
(Common to all SHARCs) Must be asserted by a host processor to request control
of the AD14060/AD14060L ’s external bus. When
HBR
is asserted in a multiprocessing system, the
ADSP-2106x that is bus master will relinquish the bus and assert
HBG
. T o relinquish the bus, the
ADSP-2106x places the address, data, select, and strobe lines in a high impedance state.
HBR
has priority
over all ADSP-2106x bus requests (
BR
6-1
) in a multiprocessing system.
Host Bus Grant.
(Common to all SHARCs)
Acknowledges an
HBR
bus request, indicating that the
host processor may take control of the external bus.
HBG
is asserted (held low) by the AD14060/AD14060L
until
HBR
is released. In a multiprocessing system,
HBG
is output by the ADSP-2106x bus master and is
monitored by all others.
Chip Select.
Asserted by host processor to select SHARC_A.
Chip Select.
Asserted by host processor to select SHARC_B.
Chip Select.
Asserted by host processor to select SHARC_C.
Chip Select.
Asserted by host processor to select SHARC_D.
Host Bus Acknowledge.
(Common to all SHARCs)
T he AD14060/AD14060L deasserts REDY (low)
to add wait states to an asynchronous access of its internal memory or IOP registers by a host. Open drain
output (O/D) by default; can be programmed in ADREDY bit of SYSCON register of individual ADSP-
21060s to be active drive (A/D). REDY will only be output if the CS and
HBR
inputs are asserted.
Multiprocessing Bus Requests.
(Common to all SHARCs)
Used by multiprocessing ADSP-2106xs to
arbitrate for bus mastership. An ADSP-2106x only drives its own
BR
x line (corresponding to the value of
its ID2-0 inputs) and monitors all others. In a multiprocessor system with less than six ADSP-2106xs, the
unused
BR
x pins should be pulled high;
BR
4-1
must not be pulled high or low because they are outputs.
Rotating Priority Bus Arbitration Select.
(Common to all SHARCs)
When RPBA is high, rotating
priority for multiprocessor bus arbitration is selected. When RPBA is low, fixed priority is selected. T his
signal is a system configuration selection that must be set to the same value on every ADSP-2106x. If the
value of RPBA is changed during system operation, it must be changed in the same CLK IN cycle on
every ADSP-2106x.
Core Priority Access.
(y = SHARC_A, B, C, D) Asserting its CPA pin allows the core processor of an
ADSP-2106x bus slave to interrupt background DMA transfers and gain access to the external bus.
CPA is an open drain output that is connected to all ADSP-2106x in the system if this function is
required. T he CPA pin of each internal ADSP-21060 is brought out individually. T he CPA pin has
an internal 5 k
pull-up resistor. If core access priority is not required in a system, the CPA pin
should be left unconnected.
Data T ransmit
(Common Serial Ports 0 to all SHARCs, T DM). DT pin has a 50 k
internal pull-up
resistor.
Data Receive
(Common Serial Ports 0 to all SHARCs, T DM). DR pin has a 50 k
internal pull-up
resistor.
T ransmit C lock
(Common Serial Ports 0 to all SHARCs, T DM). T CL K pin has a 50 k
internal
pull-up resistor.
Receive Clock
(Common Serial Ports 0 to all SHARCs, T DM). RCLK pin has a 50 k
internal pull-up
resistor.
T ransmit Frame Sync
(Common Serial Ports 0 to all SHARCs, T DM).
Receive Frame Sync
(Common Serial Ports 0 to all SHARCs, T DM).
Data T ransmit
(Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D) DT pin
has a 50 k
internal pull-up resistor.
Data Receive
(Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D) DR pin
has a 50 k
internal pull-up resistor.
HBR
I/A
HBG
I/O
CSA
CSB
CSC
CSD
REDY (O/D)
I/A
I/A
I/A
I/A
O
BR
6-1
I/O/S
RPBA
I/S
CPA
y (O/D)
I/O
DT 0
O/T
DR0
I
T CLK 0
I/O
RCLK 0
I/O
T FS0
RFS0
DT y1
I/O
I/O
O/T
DRy1
I
相關(guān)PDF資料
PDF描述
AD14060 ECONOLINE: RD & RC - Dual Output from a Single Input Rail- 1kVDC & 2kVDC Isolation- Power Sharing on Output- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 86%
AD14060L ECONOLINE: RD & RC - Dual Output from a Single Input Rail- 1kVDC & 2kVDC Isolation- Power Sharing on Output- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 86%
AD14060LBF-4 Quad-SHARC DSP Multiprocessor Family
AD14160KB-4 Quad-SHARC DSP Multiprocessor Family
AD14160 Quad-SHARC DSP Multiprocessor Family
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD14060L 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad-SHARC DSP Multiprocessor Family
AD14060LBF-4 功能描述:IC DSP CMOS 32BIT 308CQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:SHARC® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤
AD14160 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad-SHARC DSP Multiprocessor Family
AD14160BB-4 制造商:Rochester Electronics LLC 功能描述:- Bulk
AD14160KB-4 制造商:Rochester Electronics LLC 功能描述:- Bulk
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