參數(shù)資料
型號(hào)： AD14060BF-4
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號(hào)處理
英文描述： Quad-SHARC DSP Multiprocessor Family
中文描述： 48-BIT, 40 MHz, OTHER DSP, CQFP308
封裝： CERAMIC, QFP-308
文件頁(yè)數(shù)： 27/44頁(yè)
文件大小： 744K
代理商： AD14060BF-4
AD14060/AD14060L
–27–
REV. A
5 V
3.3 V
Parameter
Min
Max
Min
Max
Units
Timing Requirements:
t
ST SCK
t
HT SCK
SBTS
Setup Before CLK IN
SBTS
Hold Before CLK IN
12 + DT /2
12 + DT /2
ns
ns
5.5 + DT /2
5.5 + DT /2
Switching Characteristics:
t
MIENA
t
MIENS
t
MIENHG
t
MIT RA
t
MIT RS
t
MIT RHG
t
DAT EN
t
DAT T R
t
ACK EN
t
ACK T R
t
ADCEN
t
ADCT R
t
MT RHBG
t
MENHBG
Address/Select Enable After CLK IN
Strobes Enable After CLK IN
1
HBG
Enable After CLK IN
Address/Select Disable After CLK IN
Strobes Disable After CLK IN
1
HBG
Disable After CLK IN
Data Enable After CLK IN
2
Data Disable After CLK IN
2
ACK Enable After CLK IN
2
ACK Disable After CLK IN
2
ADRCLK Enable After CLK IN
ADRCLK Disable After CLK IN
Memory Interface Disable Before
HBG
Low
3
Memory Interface Enable After
HBG
High
3
–1.5 – DT /8
–1.5 – DT /8
–1.5 – DT /8
–1.25 – DT /8
–1.5 – DT /8
–1.5 – DT /8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1 – DT /4
2.5 – DT /4
3 – DT /4
1 – DT /4
2.5 – DT /4
3 – DT /4
9 + 5DT /16
0 – DT /8
7.5 + DT /4
–1 – DT /8
–2 – DT /8
9 + 5DT /16
0 – DT /8
7.5 + DT /4
–1 – DT /8
–2 – DT /8
8 – DT /8
8 – DT /8
7 – DT /8
7 – DT /8
9 – DT /4
9 – DT /4
–1 + DT /8
18.5 + DT
–1 + DT /8
18.5 + DT
NOT ES
1
Strobes =
RD
,
WR
,
SW
, PAGE,
DMAG
.
2
In addition to bus master transition cycles, these specs also apply to bus master and bus slave synchronous read/write.
3
Memory Interface = Address,
RD
,
WR
,
MS
x,
SW
,
HBG
, PAGE,
DMAGx
,
BMS
(in EPROM boot mode).
T hree-State T iming—Bus Master, Bus Slave,
HBR
,
SBTS
T hese specifications show how the memory interface is disabled
(stops driving) or enabled (resumes driving) relative to CLK IN
and the
SBTS
pin. T his timing is applicable to bus master tran-
sition cycles (BT C) and host transition cycles (HT C) as well as
the
SBTS
pin.
CLKIN
SBTS
ACK
MEMORY
INTERFACE
t
MENHBG
t
MTRHBG
HBG
MEMORY INTERFACE = ADDRESS,
RD
,
WR
,
MS
x,
SW
,
HBG
, PAGE,
DMAG
x.
BMS
(IN EPROM BOOT MODE)
t
MITRA,
t
MITRS,
t
MITRHG
t
STSCK
t
HTSCK
t
DATTR
t
DATEN
t
ACKTR
t
ACKEN
t
ADCTR
t
ADCEN
ADRCLK
DATA
t
MIENA,
t
MIENS,
t
MIENHG
MEMORY
INTERFACE
Figure 20. Three-State Timing
相關(guān)PDF資料
PDF描述
AD14060 ECONOLINE: RD & RC - Dual Output from a Single Input Rail- 1kVDC & 2kVDC Isolation- Power Sharing on Output- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 86%
AD14060L ECONOLINE: RD & RC - Dual Output from a Single Input Rail- 1kVDC & 2kVDC Isolation- Power Sharing on Output- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 86%
AD14060LBF-4 Quad-SHARC DSP Multiprocessor Family
AD14160KB-4 Quad-SHARC DSP Multiprocessor Family
AD14160 Quad-SHARC DSP Multiprocessor Family
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD14060L 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad-SHARC DSP Multiprocessor Family
AD14060LBF-4 功能描述:IC DSP CMOS 32BIT 308CQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:SHARC® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤
AD14160 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad-SHARC DSP Multiprocessor Family
AD14160BB-4 制造商:Rochester Electronics LLC 功能描述:- Bulk
AD14160KB-4 制造商:Rochester Electronics LLC 功能描述:- Bulk
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