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參數(shù)資料
| 型號： | AD14060BF-4 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Quad-SHARC DSP Multiprocessor Family |
| 中文描述： | 48-BIT, 40 MHz, OTHER DSP, CQFP308 |
| 封裝： | CERAMIC, QFP-308 |
| 文件頁數(shù)： | 18/44頁 |
| 文件大?。?/td> | 744K |
| 代理商： | AD14060BF-4 |
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AD14060/AD14060L
–18–
REV. A
5 V
3.3 V
Parameter
Min
Max
Min
Max
Units
Timing Requirements:
t
DAD
t
DRLD
t
HDA
t
HDRH
t
DAAK
t
DSAK
Address, Delay to Data Valid
1, 4
RD
Low to Data Valid
1
Data Hold from Address
2
Data Hold from
RD
High
2
ACK Delay from Address
3, 4
ACK Delay from
RD
Low
3
17.5 + DT + W
11.5 + 5DT /8 + W
17.5 + DT + W
11.5 + 5DT /8 + W
ns
ns
ns
ns
ns
ns
1
2.5
1
2.5
13.5 + 7DT /8 + W
7.5 + DT /2 + W
13.5 + 7DT /8 + W
7.5 + DT /2 + W
Switching Characteristics:
t
DRHA
Address Hold After
RD
High
t
DARL
Address to
RD
Low
4
t
RW
RD
Pulsewidth
t
RWR
RD
High to
WR
,
RD
,
DMAGx
Low
t
SADADC
Address Setup Before ADRCLK High
4
–0.5 + H
1.5 + 3DT /8
12.5 + 5DT /8 + W
8 + 3DT /8 + HI
–0.5 + DT /4
–0.5 + H
1.5 + 3DT /8
12.5 + 5DT /8 + W
8 + 3DT /8 + HI
–0.5 + DT /4
ns
ns
ns
ns
ns
W = (number of wait states specified in WAIT register)
×
t
CK .
HI = t
CK
(if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
H = t
CK
(if an address hold cycle occurs as specified in WAIT register; otherwise H = 0).
NOT ES
1
Data Delay/Setup: User must meet t
DAD
or t
or synchronous spec t
.
2
Data Hold: User must meet t
HDA
or t
HDRH
or synchronous spec t
HDAT I
. See System Hold T ime Calculation under T est Conditions for the calculation of hold times
given capacitive and dc loads.
3
ACK Delay/Setup: User must meet t
or t
or synchronous specification t
SACK C
.
4
For
MS
x,
SW
,
BMS
, the falling edge is referenced.
WR,
DMAG
ACK
DATA
RD
ADDRESS
MS
x,
SW
BMS
t
DARL
t
RW
t
DAD
t
SADADC
t
DAAK
t
HDRH
t
HDA
t
RWR
t
DRLD
ADRCLK
(OUT)
t
DRHA
t
DSAK
Figure 14. Memory Read—Bus Master
Memory Read—Bus Master
Use these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) without reference to
CL K IN. T hese specifications apply when the AD14060/
AD14060L is the bus master accessing external memory space.
T hese switching characteristics also apply for bus master syn-
chronous read/write timing (see Synchronous Read/Write – Bus
Master below). If these timing requirements are met, the syn-
chronous read/write timing can be ignored (and vice versa).
相關(guān)PDF資料 |
PDF描述 |
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| AD14060 | ECONOLINE: RD & RC - Dual Output from a Single Input Rail- 1kVDC & 2kVDC Isolation- Power Sharing on Output- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 86% |
| AD14060L | ECONOLINE: RD & RC - Dual Output from a Single Input Rail- 1kVDC & 2kVDC Isolation- Power Sharing on Output- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 86% |
| AD14060LBF-4 | Quad-SHARC DSP Multiprocessor Family |
| AD14160KB-4 | Quad-SHARC DSP Multiprocessor Family |
| AD14160 | Quad-SHARC DSP Multiprocessor Family |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD14060L | 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad-SHARC DSP Multiprocessor Family |
| AD14060LBF-4 | 功能描述:IC DSP CMOS 32BIT 308CQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:SHARC® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| AD14160 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad-SHARC DSP Multiprocessor Family |
| AD14160BB-4 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD14160KB-4 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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