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參數(shù)資料
| 型號(hào)： | AD14060BF-4 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | Quad-SHARC DSP Multiprocessor Family |
| 中文描述： | 48-BIT, 40 MHz, OTHER DSP, CQFP308 |
| 封裝： | CERAMIC, QFP-308 |
| 文件頁(yè)數(shù)： | 23/44頁(yè) |
| 文件大?。?/td> | 744K |
| 代理商： | AD14060BF-4 |
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AD14060/AD14060L
–23–
REV. A
5 V
3.3 V
Parameter
Min
Max
Min
Max
Units
Timing Requirements:
t
HBGRCSV
t
SHBRI
t
HHBRI
t
SHBGI
t
HHBGI
t
SBRI
t
HBRI
t
SRPBAI
t
HRPBAI
HBG
Low to
RD
/
WR
/
CS
Valid
1
HBR
Setup Before CLK IN
2
HBR
Hold Before CLK IN
2
HBG
Setup Before CLK IN
HBG
Hold Before CLK IN High
BR
x,
CPA
Setup Before CLK IN
3
BR
x,
CPA
Hold Before CLK IN High
RPBA Setup Before CLK IN
RPBA Hold Before CLK IN
19.5 + 5DT /4
19.5 + 5DT /4
ns
ns
ns
ns
ns
ns
ns
ns
ns
20 + 3DT /4
20 + 3DT /4
13.5 + 3DT /4
13.5 + 3DT /4
13 + DT /2
13 + DT /2
5.5 + DT /2
5.5 + DT /2
13 + DT /2
13 + DT /2
5.5 + DT /2
5.5 + DT /2
20 + 3DT /4
20 + 3DT /4
11.5 + 3DT /4
11.5 + 3DT /4
Switching Characteristics:
t
DHBGO
HBG
Delay After CLK IN
t
HHBGO
HBG
Hold After CLK IN
t
DBRO
BR
x Delay After CLK IN
t
HBRO
BR
x Hold After CLK IN
t
DCPAO
CPA
Low Delay After CLK IN
t
T RCPA
CPA
Disable After CLK IN
t
DRDYCS
REDY (O/D) or (A/D) Low from
CS
and
HBR
Low
4
t
T RDYHG
REDY (O/D) Disable or REDY (A/D) High from
HBG
4
t
ARDYT R
REDY (A/D) Disable from
CS
or
HBR
High
4
8 – DT /8
8 – DT /8
ns
ns
ns
ns
ns
ns
ns
ns
ns
–2 – DT /8
–2 – DT /8
8 – DT /8
8 – DT /8
–2 – DT /8
–2 – DT /8
9 – DT /8
5.5 – DT /8
9.5
9 – DT /8
5.5 – DT /8
10.25
–2 – DT /8
–2 – DT /8
44 + 27DT /16
44 + 27DT /16
11
11
NOT ES
1
For first asynchronous access after
HBR
and
CS
asserted, ADDR
31–0
must be a non-MMS value 1/2 t
CK
before
RD
or
WR
goes low or by t
HBGRCSV
after HBG goes
low. T his is easily accomplished by driving an upper address signal high when
HBG
is asserted.
2
Only required for recognition in the current cycle.
3
CPA
assertion must meet the setup to CLK IN; deassertion does not need to meet the setup to CLK IN.
4
(O/D) = open drain, (A/D) = active drive.
Multiprocessor Bus Request and Host Bus Request
Use these specifications for passing of bus mastership between
multiprocessing ADSP-2106x’s (
BR
x) or a host processor
(
HBR
,
HBG
).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD14060 | ECONOLINE: RD & RC - Dual Output from a Single Input Rail- 1kVDC & 2kVDC Isolation- Power Sharing on Output- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 86% |
| AD14060L | ECONOLINE: RD & RC - Dual Output from a Single Input Rail- 1kVDC & 2kVDC Isolation- Power Sharing on Output- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 86% |
| AD14060LBF-4 | Quad-SHARC DSP Multiprocessor Family |
| AD14160KB-4 | Quad-SHARC DSP Multiprocessor Family |
| AD14160 | Quad-SHARC DSP Multiprocessor Family |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD14060L | 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad-SHARC DSP Multiprocessor Family |
| AD14060LBF-4 | 功能描述:IC DSP CMOS 32BIT 308CQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:SHARC® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤(pán) |
| AD14160 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad-SHARC DSP Multiprocessor Family |
| AD14160BB-4 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD14160KB-4 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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