參數(shù)資料
型號： AD14060BF-4
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號處理
英文描述： Quad-SHARC DSP Multiprocessor Family
中文描述： 48-BIT, 40 MHz, OTHER DSP, CQFP308
封裝： CERAMIC, QFP-308
文件頁數(shù)： 25/44頁
文件大小： 744K
代理商： AD14060BF-4
AD14060/AD14060L
–25–
REV. A
5 V
3.3 V
Parameter
Min
Max
Min
Max
Units
Read Cycle
Timing Requirements:
t
SADRDL
t
HADRDH
t
WRWH
t
DRDHRDY
t
DRDHRDY
Address Setup/
CS
Low Before
RD
Low
1
Address Hold/
CS
Hold Low After
RD
RD
/
WR
High Width
RD
High Delay After REDY (O/D) Disable
RD
High Delay After REDY (A/D) Disable
0.5
0.5
6
0.5
0.5
0.5
0.5
6
0.5
0.5
ns
ns
ns
ns
ns
Switching Characteristics:
t
SDAT RDY
t
DRDYRDL
t
RDYPRD
t
HDARWH
Data Valid Before REDY Disable from Low
REDY (O/D) or (A/D) Low Delay After
RD
Low
REDY (O/D) or (A/D) Low Pulsewidth for Read
Data Disable After
RD
High
1.5
1.5
ns
ns
ns
ns
11
11.5
45 + DT
1.5
45 + DT
1.5
9
9.5
Write Cycle
Timing Requirements:
t
SCSWRL
t
HCSWRH
t
SADWRH
t
HADWRH
t
WWRL
t
WRWH
t
DWRHRDY
t
SDAT WH
t
HDAT WH
CS
Low Setup Before
WR
Low
CS
Low Hold After
WR
High
Address Setup Before
WR
High
Address Hold After
WR
High
WR
Low Width
RD
/
WR
High Width
WR
High Delay After REDY (O/D) or (A/D) Disable
Data Setup Before
WR
High
Data Hold After
WR
High
0.5
0.5
5.5
2.5
7
6
0.5
5.5
1.5
0.5
0.5
5.5
2.5
7
6
0.5
5.5
1.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
Switching Characteristics:
t
DRDYWRL
t
RDYPWR
t
SRDYCK
REDY (O/D) or (A/D) Low Delay After
WR
/
CS
Low
REDY (O/D) or (A/D) Low Pulsewidth for Write
REDY (O/D) or (A/D) Disable to CLK IN
11
11.5
ns
ns
ns
15
1 + 7DT /16
15
0 + 7DT /16
9 + 7DT /16
8 + 7DT /16
NOT E
1
Not required if
RD
and address are valid t
HBGRCSV
after
HBG
goes low. For first access after
HBR
asserted, ADDR
31–0
must be a non-MMS value 1/2 t
CLK
before
RD
or
WR
goes low or by t
HBGRCSV
after
HBG
goes low. T his is easily accomplished by driving an upper address signal high when
HBG
is asserted. For address bits to be
driven during asynchronous host accesses, see T able 8.2 of the
ADSP-2106x SHARC User’s Manual
.
CLKIN
REDY (O/D)
O/D = OPEN DRAIN, A/D = ACTIVE DRIVE
t
SRDYCK
REDY (A/D)
Figure 19a. Synchronous REDY Timing
Asynchronous Read/Write—Host to AD14060/AD14060L
Use these specifications for asynchronous host processor accesses
of an AD14060/AD14060L, after the host has asserted
CS
and
HBR
(low). After
HBG
is returned by the AD14060/
AD14060L, the host can drive the
RD
and
WR
pins to access
the AD14060/AD14060L’s internal memory or IOP registers.
HBR
and
HBG
are assumed low for this timing.
相關(guān)PDF資料
PDF描述
AD14060 ECONOLINE: RD & RC - Dual Output from a Single Input Rail- 1kVDC & 2kVDC Isolation- Power Sharing on Output- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 86%
AD14060L ECONOLINE: RD & RC - Dual Output from a Single Input Rail- 1kVDC & 2kVDC Isolation- Power Sharing on Output- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 86%
AD14060LBF-4 Quad-SHARC DSP Multiprocessor Family
AD14160KB-4 Quad-SHARC DSP Multiprocessor Family
AD14160 Quad-SHARC DSP Multiprocessor Family
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD14060L 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad-SHARC DSP Multiprocessor Family
AD14060LBF-4 功能描述:IC DSP CMOS 32BIT 308CQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:SHARC® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤
AD14160 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad-SHARC DSP Multiprocessor Family
AD14160BB-4 制造商:Rochester Electronics LLC 功能描述:- Bulk
AD14160KB-4 制造商:Rochester Electronics LLC 功能描述:- Bulk
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