參數(shù)資料
型號: a8259
廠商: Altera Corporation
英文描述: Programmable Interrupt Controller(可編程中斷控制器)
中文描述: 可編程中斷控制器(可編程中斷控制器)
文件頁數(shù): 4/24頁
文件大?。?/td> 220K
代理商: A8259
60
Altera Corporation
a8259 Programmable Interrupt Controller Data Sheet
The
casin[2..0]
and
casout[2..0]
buses, and
nsp
and
cas_en
pins
are used to implement the cascade interface. These pins are used when
more than one
a8259
functions are interconnected in a master/ slave
configuration, expanding the number of interrupts from 8 up to 64.
Programming
& Initialization
The
a8259
operation depends on initial programming. Two types of
command words are used for programming the
a8259
: initialization
command words (ICWs) and operation command words (OCWs). ICWs
are used to load the
a8259
internal control registers, while the OCWs
permit the microprocessor to initiate variations in the basic operating
modes defined by the ICW registers.
Table 2
summarizes how to access
the ICW and OCW registers for programming and initialization (for more
information on ICW and OCW registers, see
“Register Descriptions” on
page 62
).
Note:
(1)
“Don’t Care” indicates that the bit has no address significance for this register access method. However, the bit will
usually have data significance.
To begin an initialization sequence, the
a0
pin must be low, and bit 4 of
the
din[7..0]
bus must be high during a valid write cycle.
Figure 3
shows the
a8259
initialization sequence flow diagram.
Table 2. ICW & OCW Register Access for Programmng & Initialization
Note (1)
Register
Mnemonics
Description
Access Method
A0
D4
D3
ICW 1
0
1
Don’t Care A write with A0 low and D4 high is
interpreted as the beginning of an
initialization sequence.
Don’t Care This register always follows ICW 1.
Don’t Care The use of this register depends on
the value of SINGLE (see
Figure 3
on
page 61
).
Don’t Care The use of this register depends on
the value of IC4 (see
Figure 3
on
page 61
).
Don’t Care These registers can be accessed
randomly (see
“Operation Command
Word Registers” on page 65
for
more details).
Sequential access
which starts with ICW 1
and timed by the pulsing
nwr
signal.
ICW 2
ICW 3
1
1
Don’t Care
Don’t Care
ICW 4
1
Don’t Care
OCW 1
OCW 2
OCW 3
1
0
0
Don’t Care
0
0
Random access
0
1
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