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參數(shù)資料
| 型號： | a8259 |
| 廠商： | Altera Corporation |
| 英文描述： | Programmable Interrupt Controller(可編程中斷控制器) |
| 中文描述： | 可編程中斷控制器（可編程中斷控制器） |
| 文件頁數(shù)： | 20/24頁 |
| 文件大?。?/td> | 220K |
| 代理商： | A8259 |
76
Altera Corporation
a8259 Programmable Interrupt Controller Data Sheet
Figure 8
shows timing waveforms of the poll mode.
Figure 8. Poll Mode Timng Waveforms for Bit 2 of OCW 3
X indicates “Dont Care.” VD indicates “Vector Data.”
Operating
Modes &
Sequence of
Events
The
a8259
can operate in four different modes:
I
I
I
I
Fully nested mode
Cascade mode
Special fully nested mode
Buffered mode
Fully Nested Mode
The fully nested mode is the default mode, after the master clear. The
a8259
will enter this mode when initialization is completed, unless
another mode is specifically programmed. When the
a8259
is in fully
nested mode, the following sequence of events occurs:
1.
The interrupt requests are prioritized from 0 (highest priority) to 7
(lowest priority).
2.
When an interrupt request is acknowledged, the highest priority,
unmasked request is determined, the corresponding bit in the ISR is
set, and the IRR bit is reset. While the ISR bit is being set, further
interrupts from lower priority sources are ignored. Interrupts from
higher priority sources are clocked, causing the
int
signal to remain
active until the interrupt is serviced.
clk
Edge-triggered
interrupt request
Level-triggered
interrupt request
or
int
dout
nrd
nwr
X
X
VD
dout[7..0]
Level-triggered interrupt
request is clocked by the
falling edge of nrd.
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