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參數(shù)資料
| 型號(hào)： | a8259 |
| 廠商： | Altera Corporation |
| 英文描述： | Programmable Interrupt Controller(可編程中斷控制器) |
| 中文描述： | 可編程中斷控制器（可編程中斷控制器） |
| 文件頁數(shù)： | 12/24頁 |
| 文件大?。?/td> | 220K |
| 代理商： | A8259 |
68
Altera Corporation
a8259 Programmable Interrupt Controller Data Sheet
Table 12
describes the OCW 3 register format.
Note:
(1)
Enable special mask mode.
Table 13
describes the read register commands for bits 0 and 1 of the
OCW 3 command register.
Table 14
describes the special mask mode commands for bits 5 and 6 of the
OCW 3 command register.
Table 12. OCW 3 Register Format
Bit
Decode
Description
0
1
RIS
RR
Read register command. These bits control which status
register will be accessed on the next read cycle (see
Table 13
).
When this bit is high and RR is high, the
a8259
enters
the poll mode; the next
nrd
cycle ends the poll mode
(see
“Poll Command” on page 75
).
These bits are used as address decode. Bit 4 must be
low and bit 3 must be high.
2
P
3
4
5
6
1
0
SMM
ESMM
(1)
Special mask mode. These bits are used to enable, set,
and clear the special mask mode function (see
Table 14
).
This bit is unused and should be tied to
GND
.
7
0
Table 13. Read Register Commands for Bits 0 & 1 of OCW 3
RR
RIS
Command
0
0
1
1
0
1
0
1
No action
No action
Read interrupt request register (IRR) on next read cycle
Read in-service register (ISR) on next read cycle
Table 14. Read Register Commands for Bits 0 & 1 of OCW 3
Bit 6 ESMM
Bit 5 SMM
Command
0
0
1
1
0
1
0
1
No action
No action
Reset special mask
Set special mask
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