Altera Corporation
79
a8259 Programmable Interrupt Controller Data Sheet
To complete the interrupt service and ensure that all interrupts from the
slave have been serviced, the microprocessor sends a non-specific EOI
command to the slave and reads the slave’s interrupt request register for
active low signals. If the interrupt request register is low, a non-specific
EOI command is issued to the master. Otherwise, the master services the
pending interrupt request.
Buffered Mode
The buffered mode was originally intended to support board designs
where tri-state buffers were needed to drive the data bus. The
a8259
has
separate
nsp
and
nen
signals, and the
nen
signal is always available.
Instead of using the
nsp
signal, the buffered mode can determine the
master/ slave configuration by using bits 2 and 3 of the ICW 4 command
register.
Variations &
Clarifications
The following characteristics distinguish the Altera
a8259
function from
the Intel 8259A device:
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A master clear is provided with the
a8259
.
A clock signal has been added, and synchronous design rules have
been incorporated to improve operation and reliability. All input
signals except
nmrst
and
ir
should be synchronous to the clock
signal. All inputs must be asserted for one clock cycle to ensure
reliable operation.
Bidirectional I/ O pins are split into separate inputs, outputs, and
corresponding tri-state control lines. This features makes the
a8259
compatible with the bus or multiplexer scheme used internally in a
design.
The
dout[7..0]
,
casout[2..0]
,
int
,
cas_en
,
en
, and
nen
outputs are driven by complex logic structures and are prone to
glitches. If appropriate, these signals should be registered in a target
application.
Because the
a8259
can be used in various Altera architectures, no
timing information is included in this data sheet.
Automatic EOI in slave mode is implemented within the
a8259
.
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