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參數(shù)資料
| 型號： | a8259 |
| 廠商： | Altera Corporation |
| 英文描述： | Programmable Interrupt Controller(可編程中斷控制器) |
| 中文描述： | 可編程中斷控制器（可編程中斷控制器） |
| 文件頁數(shù)： | 13/24頁 |
| 文件大小： | 220K |
| 代理商： | A8259 |
Altera Corporation
69
a8259 Programmable Interrupt Controller Data Sheet
Interrupt Registers
The
a8259
contains two interrupt registers:
I
I
Interrupt request register (IRR)
In-service register (ISR)
Interrupt Request Register
The IRR stores all interrupts that are requesting service. In edge-triggered
mode (when bit 3 of ICW 1 is low), each
ir
pin is synchronized to the
clk
signal. Positive-edge detection is performed, and the result is clocked into
the IRR.
In level-triggered mode (when bit 3 of ICW 1 is high), each
ir
signal is
clocked directly into the IRR. The falling edge of the first
ninta
signal
from the microprocessor freezes the IRR so all interrupts can be evaluated.
The level of an
ir
signal from the microprocessor must be maintained
until after the falling edge of the
ninta
signal. Interrupt handshaking
protocol must be completed before the next interrupt can be received.
Table 15
shows the IRR format.
In-Service Register
The ISR stores the interrupt level currently being serviced. Data is enabled
by the first
ninta
signal of the interrupt acknowledge sequence. In AEIO
mode, data is reset upon the final rising edge of the
ninta
signal in the
interrupt sequence. Otherwise, the microprocessor must issue an EOI
command by writing the appropriate value to the OCW 2 command
register.
Table 16
shows the ISR format.
Table 15. IRR Format
Bit
Decode
0
1
2
3
4
5
6
7
IR0
IR1
IR2
IR3
IR4
IR5
IR6
IR7
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