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參數(shù)資料
| 型號： | a8259 |
| 廠商： | Altera Corporation |
| 英文描述： | Programmable Interrupt Controller(可編程中斷控制器) |
| 中文描述： | 可編程中斷控制器（可編程中斷控制器） |
| 文件頁數(shù)： | 15/24頁 |
| 文件大小： | 220K |
| 代理商： | A8259 |
Altera Corporation
71
a8259 Programmable Interrupt Controller Data Sheet
Notes to tables:
(1)
Interval = 4 (bit 2 of ICW 1 is high).
(2)
A7 through A5 are derived from the contents of bits 5, 6, and 7 of ICW 1.
(3)
Interval = 8 (bit 2 of ICW 1 is low).
6.
The upper eight interrupt vector address bytes are released on the
falling edge of the second
ninta
pulse. The contents of the upper
eight interrupt vector address bytes are always derived from the
contents of ICW 2. See
Table 19
.
7.
In AEOI mode, a bit in the ISR is reset on the rising edge of the last
ninta
pulse. When not in AEOI mode, an appropriate EOI
command must be issued to end the interrupt sequence.
Table 17. Contents of the First Interrupt Vector Bytes
Notes (1)
,
(2)
ir
dout7
dout6
dout5
dout4
dout3
dout2
dout1
dout0
7
6
5
4
3
2
1
0
A7
A7
A7
A7
A7
A7
A7
A7
A6
A6
A6
A6
A6
A6
A6
A6
A5
A5
A5
A5
A5
A5
A5
A5
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 18. Contents of the First Interrupt Vector Bytes
Notes (2)
,
(3)
ir
dout7
dout6
dout5
dout4
dout3
dout2
dout1
dout0
7
6
5
4
3
2
1
0
A7
A7
A7
A7
A7
A7
A7
A7
A6
A6
A6
A6
A6
A6
A6
A6
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 19. Contents of the Second Interrupt Vector Bytes
dout7
dout6
dout5
dout4
dout3
dout2
dout1
dout0
A15
A14
A13
A12
A11
A10
A9
A8
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