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參數(shù)資料
| 型號(hào)： | a8259 |
| 廠商： | Altera Corporation |
| 英文描述： | Programmable Interrupt Controller(可編程中斷控制器) |
| 中文描述： | 可編程中斷控制器（可編程中斷控制器） |
| 文件頁數(shù)： | 21/24頁 |
| 文件大?。?/td> | 220K |
| 代理商： | A8259 |
Altera Corporation
77
a8259 Programmable Interrupt Controller Data Sheet
3.
During the appropriate handshaking sequence using the
inta
and
ninta
signals, the interrupt vector information is placed on the
dout[7..0]
bus.
4.
In AEOI mode, the ISR bit is reset on the rising edge of the last
ninta
pulse. When not in AEOI mode, an appropriate EOI
command is issued to end the interrupt sequence.
Cascade Mode
The cascade mode provides easy expansion of the
a8259
. In this mode, a
single
a8259
is configured as a master, while other
a8259
functions
(from 1 to 8
a8259
functions) are configured as slaves. The
int
signal of
each slave is connected to an
ir
input on the master. The master’s
int
signal serves as an interrupt to the microprocessor. The master’s
casout[2..0]
bus is connected to a slave’s
casin[2..0]
bus. Each
a8259
has a unique
ncs
signal and all other inputs to the
a8259
are
connected in parallel.
When a slave receives an interrupt, the master asserts its
int
signal. The
master enables the slave by placing the slave’s address on the
casout[2..0]
bus at the rising edge of the first
ninta
pulse. The slave
is then responsible for completing the
int
and
ninta
handshaking
required by the interrupt sequence. The slave will place its interrupt
vector information on the
dout[7..0]
bus as required by the interrupt
sequence.
3-Byte Interrupt Sequence in Cascade Mode
For a 3-byte interrupt sequence in cascade mode, the handshaking
between the
int
and
ninta
signals is as follows:
1.
The master clocks the ISR bit that corresponds to the slave input on
the falling edge of the first
ninta
pulse. The master also
simultaneously resets the IRR bit and places a fixed vector opcode of
binary
11001101
on the
dout[7..0]
bus. The vector opcode
indicates that the two bytes that follow will contain the interrupt
vector. The master enables the slave by placing the slave’s address
on the
casout[7..0]
bus at the rising edge of the first
ninta
pulse.
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