- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375157 > A81L801TG-70IF (AMIC Technology Corporation) Stacked Multi-chip Package (MCP) 1 M X 8 Bit / 512K X 16 Bit Boot Sector Flash Memory and 128K x 8 Low Voltage CMOS SRAM PDF資料下載
參數(shù)資料
| 型號： | A81L801TG-70IF |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | Stacked Multi-chip Package (MCP) 1 M X 8 Bit / 512K X 16 Bit Boot Sector Flash Memory and 128K x 8 Low Voltage CMOS SRAM |
| 中文描述： | 堆疊式多芯片封裝（MCP）1的MX 8位/ 16位為512k ×引導(dǎo)扇區(qū)閃存和128K × 8 SRAM的低電壓的CMOS |
| 文件頁數(shù)： | 43/47頁 |
| 文件大?。?/td> | 705K |
| 代理商： | A81L801TG-70IF |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁當(dāng)前第43頁第44頁第45頁第46頁第47頁
A81L801
PRELIMINARY (March, 2005, Version 0.0)
42
AMIC Technology, Corp.
Timing Waveforms (continued)
Write Cycle 2
(Chip Enable Controlled)
t
WC
Address
CE_S
D
IN
t
DH
t
DW
(4)
t
CW5
t
AW
t
WR3
WE
D
OUT
t
WHZ7
t
CW5
t
AS1
Notes: 1. t
AS
is measured from the address valid to the beginning of Write.
2. A Write occurs during the overlap (t
WP
) of a low
CE_S
, and a low WE .
3. t
WR
is measured from the earliest of
CE_S
or WE going high going low to the end of the Write cycle.
4. If
the
CE_S
low
transition
occurs
the WE transition, outputs remain in a high impedance state.
5. t
CW
is measured from the later of
CE_S
going low going high to the end of Write.
6. OE is continuously low. ( OE = V
IL
)
7. Transition is measured
±
500mV from steady state. This parameter is sampled and not 100% tested.
simultaneously
with
the
WE
low
transition
or
after
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A81L801UG-70 | Stacked Multi-chip Package (MCP) 1 M X 8 Bit / 512K X 16 Bit Boot Sector Flash Memory and 128K x 8 Low Voltage CMOS SRAM |
| A81L801UG-70F | Stacked Multi-chip Package (MCP) 1 M X 8 Bit / 512K X 16 Bit Boot Sector Flash Memory and 128K x 8 Low Voltage CMOS SRAM |
| A81L801UG-70I | Stacked Multi-chip Package (MCP) 1 M X 8 Bit / 512K X 16 Bit Boot Sector Flash Memory and 128K x 8 Low Voltage CMOS SRAM |
| A81L801UG-70IF | Stacked Multi-chip Package (MCP) 1 M X 8 Bit / 512K X 16 Bit Boot Sector Flash Memory and 128K x 8 Low Voltage CMOS SRAM |
| A8205SLH-XX | LOW-DROPOUT REGULATORS - HIGH EFFICIENCY |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A81L801UG-70 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:Stacked Multi-chip Package (MCP) 1 M X 8 Bit / 512K X 16 Bit Boot Sector Flash Memory and 128K x 8 Low Voltage CMOS SRAM |
| A81L801UG-70F | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:Stacked Multi-chip Package (MCP) 1 M X 8 Bit / 512K X 16 Bit Boot Sector Flash Memory and 128K x 8 Low Voltage CMOS SRAM |
| A81L801UG-70I | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:Stacked Multi-chip Package (MCP) 1 M X 8 Bit / 512K X 16 Bit Boot Sector Flash Memory and 128K x 8 Low Voltage CMOS SRAM |
| A81L801UG-70IF | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:Stacked Multi-chip Package (MCP) 1 M X 8 Bit / 512K X 16 Bit Boot Sector Flash Memory and 128K x 8 Low Voltage CMOS SRAM |
| A-81X | 制造商:Triad Magnetics 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。